Apply high-level synthesis design and verification methodology on floating-point unit implementation

Abstract

For decades, several researchers in both academic and industrial dedicate to reduce the widen gap between technology capabilities and productivity of hardware designer. HLS (high-level synthesis) is one of the promising possibilities to speed up the product development time. In this paper, we propose a HLS framework. Then design and verify an FPU (floating-point unit) via the proposed framework. The target design goes through the entire flow from a behavioral model down to gate-level netlist. Discussion on general issues of HLS is provided as experience sharing. QoR (quality-of-result) of the framework and the FPU are also evaluated at the end of this article.