A 30dBm PA for MTC communication in 65nm CMOS technology

Abstract

In this paper the feasibility of using a fully integrated 65nm CMOS PA in future machine-type communication standards has been investigated. The integrated PA investigated shows a linear output power in VSWR 2:1 of minimum 24dBm. A VSWR of 2:1 with an associated 3.1dB front-end insertion loss corresponds to a VSWR of 5:1 at the antenna, which is a conservative number. The PAE at 1dB compression point is close to 40% for VSWR 1:1. Taking margin for modulation peak-to-average ratio of 5dB, the PAE at compression point -5dB is 31% at 2100MHz and 24% at 2600MHz. To show the possibility of multi-band operation the PA is centered at 2100MHz and then retuned to 2600MHz, indicating feasibility of a single high band PA. The gain of the two-stage PA is 27dB at 2100MHz and 24dB at 2600MHz. All simulated with a 3.3V output stage supply.