Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451029
Javier Schandy, J. Oreggioni, Leonardo Steinfeld
A DC-DC switching converter, originally included to reduce the power consumption of a Wireless Sensor Networks (WSN) node, has been proposed as the core of an on-field self-energy meter. In this paper we present a method and circuit that improves the electronics proposed by previous work by conditioning the signal from the switching converter that is connected to the microcontroller's counter. A software module that allows a WSN node to measure its own charge and current consumption was also implemented. The proposed method allows to measure the current consumption in a wide range, from 0 to 30mA, is highly linear and is ultra-low-power (the maximum current consumption is 8μA). Finally, we present a case study in which the proposed method is used to power profile a WSN node. Results show that a time-based estimation (Energest) overestimates the Clear Channel Assessment consumption for more than 10%.
{"title":"DC-DC switching converter as on-field self energy meter","authors":"Javier Schandy, J. Oreggioni, Leonardo Steinfeld","doi":"10.1109/LASCAS.2016.7451029","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451029","url":null,"abstract":"A DC-DC switching converter, originally included to reduce the power consumption of a Wireless Sensor Networks (WSN) node, has been proposed as the core of an on-field self-energy meter. In this paper we present a method and circuit that improves the electronics proposed by previous work by conditioning the signal from the switching converter that is connected to the microcontroller's counter. A software module that allows a WSN node to measure its own charge and current consumption was also implemented. The proposed method allows to measure the current consumption in a wide range, from 0 to 30mA, is highly linear and is ultra-low-power (the maximum current consumption is 8μA). Finally, we present a case study in which the proposed method is used to power profile a WSN node. Results show that a time-based estimation (Energest) overestimates the Clear Channel Assessment consumption for more than 10%.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117157449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451081
Edwin G. Carreno, C. Hernandez, O. M. Diaz, H. Gómez, C. Fajardo, H. Hernández, W. Noije, E. Roa
A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end electronics without any loss of data.
{"title":"A 3.9 compression-ratio Huffman encoding scheme for the large ion collider on 65nm and 130nm CMOS technologies","authors":"Edwin G. Carreno, C. Hernandez, O. M. Diaz, H. Gómez, C. Fajardo, H. Hernández, W. Noije, E. Roa","doi":"10.1109/LASCAS.2016.7451081","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451081","url":null,"abstract":"A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end electronics without any loss of data.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128677207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451060
A. C. Oliveira, J. Caicedo, H. Klimach, S. Bampi
In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.
{"title":"0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference","authors":"A. C. Oliveira, J. Caicedo, H. Klimach, S. Bampi","doi":"10.1109/LASCAS.2016.7451060","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451060","url":null,"abstract":"In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126327241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451032
Piotr Patronik, S. Piestrak
In this paper, we propose a new approach to use Residue Number System (RNS) to design an arithmetic coprocessing unit, which allows to parallelize execution of addition and multiplication. The chosen RNS is a 5-moduli set composed of a larger even modulus 213 and four moduli of the type 2n - 1, which all fit into the 32-bit word of the processor. The RNS operations are implemented in hardware, except for the reverse conversion which is implemented in software. Simulation experiments performed on synthesized five-operation arithmetic unit show that at a small hardware and software cost can be achieved 10% energy saving for a constant-coefficient filter application and up to 25% for the matrix multiplication, compared to executions using a positional arithmetic unit.
{"title":"Design of a low-power RNS-enhanced arithmetic unit","authors":"Piotr Patronik, S. Piestrak","doi":"10.1109/LASCAS.2016.7451032","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451032","url":null,"abstract":"In this paper, we propose a new approach to use Residue Number System (RNS) to design an arithmetic coprocessing unit, which allows to parallelize execution of addition and multiplication. The chosen RNS is a 5-moduli set composed of a larger even modulus 213 and four moduli of the type 2n - 1, which all fit into the 32-bit word of the processor. The RNS operations are implemented in hardware, except for the reverse conversion which is implemented in software. Simulation experiments performed on synthesized five-operation arithmetic unit show that at a small hardware and software cost can be achieved 10% energy saving for a constant-coefficient filter application and up to 25% for the matrix multiplication, compared to executions using a positional arithmetic unit.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123856704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451026
A. Queiroz, Luiz Carlos Macedo de Oliveira Filho
An investigation is made about the practicability of building electrostatic generators suitable for energy harvesting applications using 3D-printed electromechanical structures. The generators are based on variable capacitors, using structures similar to Bennet's doubler, or more complex charge multipliers. Normal ABS plastic is used for insulating and mechanical structures, and conductive ABS is used for conducting parts as capacitor plates. As these generators work at very high impedance levels, the relatively high resistivity of the material used as conductor has acceptably small effect, and the technique can be used as an inexpensive alternative for experimenting with generator structures.
{"title":"Energy harvesting with 3D-printed electrostatic generators","authors":"A. Queiroz, Luiz Carlos Macedo de Oliveira Filho","doi":"10.1109/LASCAS.2016.7451026","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451026","url":null,"abstract":"An investigation is made about the practicability of building electrostatic generators suitable for energy harvesting applications using 3D-printed electromechanical structures. The generators are based on variable capacitors, using structures similar to Bennet's doubler, or more complex charge multipliers. Normal ABS plastic is used for insulating and mechanical structures, and conductive ABS is used for conducting parts as capacitor plates. As these generators work at very high impedance levels, the relatively high resistivity of the material used as conductor has acceptably small effect, and the technique can be used as an inexpensive alternative for experimenting with generator structures.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114885929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451069
F. A. Castaño, A. M. Hernández, C. A. Sarmiento, A. Camacho, C. Vega, J. D. Lemos
This paper shows the design of a wearable device for measuring vital signs, oriented to monitoring applications and home health care. In order to improve the living conditions of the patient, device allows that the patient can perform their daily activities while their health is monitored. The designed device allows measuring electrocardiogram, blood oxygen saturation, non-invasive blood pressure and heart rate. This paper proposes a novel technique to reduce motion artifacts based on signals measurement redundantly, also the importance at clinic level of measuring these variables is shown. The device transmits the information wirelessly to a proprietary application for viewing, the result of used technique for reducing artifacts is shown and a prototype of the device is presented. Finally, the advantages and future improvements of the wearable monitor are discussed.
{"title":"Redundant measurement of vital signs in a wearable monitor to overcome movement artifacts in home health care environment","authors":"F. A. Castaño, A. M. Hernández, C. A. Sarmiento, A. Camacho, C. Vega, J. D. Lemos","doi":"10.1109/LASCAS.2016.7451069","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451069","url":null,"abstract":"This paper shows the design of a wearable device for measuring vital signs, oriented to monitoring applications and home health care. In order to improve the living conditions of the patient, device allows that the patient can perform their daily activities while their health is monitored. The designed device allows measuring electrocardiogram, blood oxygen saturation, non-invasive blood pressure and heart rate. This paper proposes a novel technique to reduce motion artifacts based on signals measurement redundantly, also the importance at clinic level of measuring these variables is shown. The device transmits the information wirelessly to a proprietary application for viewing, the result of used technique for reducing artifacts is shown and a prototype of the device is presented. Finally, the advantages and future improvements of the wearable monitor are discussed.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123092889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451031
J. Wernehag, W. Ahmad, H. Sjöland, O. Zander, Vanja Plicanic Samuelsson
In this paper the feasibility of using a fully integrated 65nm CMOS PA in future machine-type communication standards has been investigated. The integrated PA investigated shows a linear output power in VSWR 2:1 of minimum 24dBm. A VSWR of 2:1 with an associated 3.1dB front-end insertion loss corresponds to a VSWR of 5:1 at the antenna, which is a conservative number. The PAE at 1dB compression point is close to 40% for VSWR 1:1. Taking margin for modulation peak-to-average ratio of 5dB, the PAE at compression point -5dB is 31% at 2100MHz and 24% at 2600MHz. To show the possibility of multi-band operation the PA is centered at 2100MHz and then retuned to 2600MHz, indicating feasibility of a single high band PA. The gain of the two-stage PA is 27dB at 2100MHz and 24dB at 2600MHz. All simulated with a 3.3V output stage supply.
{"title":"A 30dBm PA for MTC communication in 65nm CMOS technology","authors":"J. Wernehag, W. Ahmad, H. Sjöland, O. Zander, Vanja Plicanic Samuelsson","doi":"10.1109/LASCAS.2016.7451031","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451031","url":null,"abstract":"In this paper the feasibility of using a fully integrated 65nm CMOS PA in future machine-type communication standards has been investigated. The integrated PA investigated shows a linear output power in VSWR 2:1 of minimum 24dBm. A VSWR of 2:1 with an associated 3.1dB front-end insertion loss corresponds to a VSWR of 5:1 at the antenna, which is a conservative number. The PAE at 1dB compression point is close to 40% for VSWR 1:1. Taking margin for modulation peak-to-average ratio of 5dB, the PAE at compression point -5dB is 31% at 2100MHz and 24% at 2600MHz. To show the possibility of multi-band operation the PA is centered at 2100MHz and then retuned to 2600MHz, indicating feasibility of a single high band PA. The gain of the two-stage PA is 27dB at 2100MHz and 24dB at 2600MHz. All simulated with a 3.3V output stage supply.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114963165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451078
J. Cabrera-Lopez, Jaime Velasco-Medina, E. Denis, Juan Felipe Briceno Calderon, Oscar Julian Gomez Guevara
The Electrical Impedance Spectroscopy (EIS) has been recently proposed as a simple non-invasive technique to characterize biological materials, and observe signals and physiological parameters. While the technique capabilities are still questioned, a simple and low-cost system based on a mixed-signal circuit is capable of performing this kind of measurements for testing different materials, like tissues with minimal effort. The system includes a DDS sine waveform generator, a voltage controlled current source, a programmable mixed-signal circuit and an Analog Front-End (AFE) for signal acquisition. From the simulation and experimental results, it is possible to say the designed system is suitable for applications that require wide frequency and load ranges, being an excellent option for EIS and Electrical Impedance Tomography (EIT) applications.
{"title":"Bioimpedance measurement using mixed-signal embedded system","authors":"J. Cabrera-Lopez, Jaime Velasco-Medina, E. Denis, Juan Felipe Briceno Calderon, Oscar Julian Gomez Guevara","doi":"10.1109/LASCAS.2016.7451078","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451078","url":null,"abstract":"The Electrical Impedance Spectroscopy (EIS) has been recently proposed as a simple non-invasive technique to characterize biological materials, and observe signals and physiological parameters. While the technique capabilities are still questioned, a simple and low-cost system based on a mixed-signal circuit is capable of performing this kind of measurements for testing different materials, like tissues with minimal effort. The system includes a DDS sine waveform generator, a voltage controlled current source, a programmable mixed-signal circuit and an Analog Front-End (AFE) for signal acquisition. From the simulation and experimental results, it is possible to say the designed system is suitable for applications that require wide frequency and load ranges, being an excellent option for EIS and Electrical Impedance Tomography (EIT) applications.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":" 37","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120827894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451003
M. Teplechuk, Franck Banag, Barry Mcadam, A. Gribben, Zakaria Mengad
A fully integrated filterless Class-D audio amplifier with direct two-cell(2S) battery connection delivering continuous 7.8Watt into 4Ohm load with 0.005% THD+N and 104dB SNR. Packaged in 9 ball WLSCP, it does not require any external components and operates in a supply range of 4-12V from a direct 2S battery. In a burst mode device achieves maximum output power of 19.6W into 4Ohm load with THD+N=20% from a 12V supply. The chip is fabricated in a standard 0.25um BCDMOS process with total chip area measuring 2.54mm2.
{"title":"A 7.8W continuous and 19.6W burst output power fully integrated 2S Class-D amplifier with 0.005% THD+N","authors":"M. Teplechuk, Franck Banag, Barry Mcadam, A. Gribben, Zakaria Mengad","doi":"10.1109/LASCAS.2016.7451003","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451003","url":null,"abstract":"A fully integrated filterless Class-D audio amplifier with direct two-cell(2S) battery connection delivering continuous 7.8Watt into 4Ohm load with 0.005% THD+N and 104dB SNR. Packaged in 9 ball WLSCP, it does not require any external components and operates in a supply range of 4-12V from a direct 2S battery. In a burst mode device achieves maximum output power of 19.6W into 4Ohm load with THD+N=20% from a 12V supply. The chip is fabricated in a standard 0.25um BCDMOS process with total chip area measuring 2.54mm2.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128512009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451094
Daniel R. Mendat, S. Chin, S. Furber, A. Andreou
We present a bio-inspired, hardware/software architecture to perform Markov Chain Monte Carlo sampling on probabilistic graphical models using energy aware hardware. We have developed algorithms and programming data flows for two recently developed multiprocessor architectures, the SpiNNaker and Parallella. We employ a neurally inspired sampling algorithm that abstracts the functionality of neurons in a biological network and exploits the neural dynamics to implement the sampling process. This algorithm maps nicely on the two hardware systems. Speedups as high as 1000 fold are achieved when performing inference using this approach, compared to algorithms running on traditional engineering workstations.
{"title":"Neuromorphic sampling on the SpiNNaker and parallella chip multiprocessors","authors":"Daniel R. Mendat, S. Chin, S. Furber, A. Andreou","doi":"10.1109/LASCAS.2016.7451094","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451094","url":null,"abstract":"We present a bio-inspired, hardware/software architecture to perform Markov Chain Monte Carlo sampling on probabilistic graphical models using energy aware hardware. We have developed algorithms and programming data flows for two recently developed multiprocessor architectures, the SpiNNaker and Parallella. We employ a neurally inspired sampling algorithm that abstracts the functionality of neurons in a biological network and exploits the neural dynamics to implement the sampling process. This algorithm maps nicely on the two hardware systems. Speedups as high as 1000 fold are achieved when performing inference using this approach, compared to algorithms running on traditional engineering workstations.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133712478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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