Hanie Ghaedrahmati, Jianfeng Xue, J. Jin, Jianjun J. Zhou
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引用次数: 0
Abstract
A 10-bit 160MS/s 20MHz bandwidth low-power noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) using a novel dynamic amplifier-based filter is presented. Thanks to noise-shaping architecture, the proposed scheme can achieve 10-bit resolution while employing only 8-bit capacitor-DAC array. The prototype ADC is designed in 40nm CMOS technology, with a peak signal-to-noise-distortion ratio (SNDR) 59 dB and 68 dB spurious-free-dynamic-range (SFDR) at 160 MS/s sampling frequency, while consuming 1 mW power from 1.1 V supply voltage. The figure-of-merit (FoM) is 34.29 fJ/conv.-step.
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