Pub Date : 2018-07-14DOI: 10.1109/CIRSYSSIM.2018.8525891
Jing Cui-Ru, Li Qian, Wu Yi-fei, Shi-Zhou Xu, Fu Qiang
With the rapid development of new energy and the energy-saving technology, three-level inverter has gradually become the core of power conversion because of its large output capacity, good dynamic performance, low harmonic content and high inversion efficiency. In the view of the inherent problem of uneven DC side voltage distribution in T type three-level inverter, this paper analyzes the influence factors of neutral point potential imbalance based on SVPWM (Space Vector Pulse width Modulation method), and establishes the midpoint average current mathematical model. According to the current state of the midpoint under different types of vector action, a self-adaptive distribution factor method is proposed, which can self-adjust according to the potential difference of the midpoint, and the expected effect is obtained in the simulation.
{"title":"Research on Neutral Point Potential Balance of Three-Level Inverter","authors":"Jing Cui-Ru, Li Qian, Wu Yi-fei, Shi-Zhou Xu, Fu Qiang","doi":"10.1109/CIRSYSSIM.2018.8525891","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525891","url":null,"abstract":"With the rapid development of new energy and the energy-saving technology, three-level inverter has gradually become the core of power conversion because of its large output capacity, good dynamic performance, low harmonic content and high inversion efficiency. In the view of the inherent problem of uneven DC side voltage distribution in T type three-level inverter, this paper analyzes the influence factors of neutral point potential imbalance based on SVPWM (Space Vector Pulse width Modulation method), and establishes the midpoint average current mathematical model. According to the current state of the midpoint under different types of vector action, a self-adaptive distribution factor method is proposed, which can self-adjust according to the potential difference of the midpoint, and the expected effect is obtained in the simulation.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525871
Yanhua Zhang, Lijie Yang, Ruirui Dang, Zhiwei Xu, Chunyi Song
A 14-bit 500-MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) for receiver application is fabricated on a 65 nm CMOS relying on correlation-based background calibrations to correct the inter-stage gain and settling errors. In order to suppress the non-linearity caused by inter-stage gain error due to insufficient amplifier gain, a new dithering technique is employed on the residual transfer function. In addition, the comparators in all stages are trimmed digitally to minimize their offset and further improve the linearity. The measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 67 dB and 88 dB after calibration at 350 MHz input signal. The ADC occupies an active area of 3 mm2 and consumes a total power of 0.9 W from 1.3 V and 2.0 V supplies.
{"title":"A 14-bit 500-MS/s SHA-less Pipelined ADC in 65nm CMOS Technology for Wireless Receiver","authors":"Yanhua Zhang, Lijie Yang, Ruirui Dang, Zhiwei Xu, Chunyi Song","doi":"10.1109/CIRSYSSIM.2018.8525871","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525871","url":null,"abstract":"A 14-bit 500-MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) for receiver application is fabricated on a 65 nm CMOS relying on correlation-based background calibrations to correct the inter-stage gain and settling errors. In order to suppress the non-linearity caused by inter-stage gain error due to insufficient amplifier gain, a new dithering technique is employed on the residual transfer function. In addition, the comparators in all stages are trimmed digitally to minimize their offset and further improve the linearity. The measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 67 dB and 88 dB after calibration at 350 MHz input signal. The ADC occupies an active area of 3 mm2 and consumes a total power of 0.9 W from 1.3 V and 2.0 V supplies.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134331440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525886
Nana Hao
Proof-of-work, as the core technology of public blockchain, requires users to pay a certain amount of work in order to create new blocks by competition. This article innovatively applies it to the train ticket market, and introduces such a mechanism at the interface of the ticketing system to prevent the system from being attacked. Based on the background of China's internet train ticketing system, this paper analyzes the internal and external attacks on the system, designs an algorithm based on proof-of-work, and expands according to the geographical location, credit rating, and system load based on different problems. However, there is a big difference in CPU performance between different computer devices, leading to the difficulty for some users with insufficient computing power to buy tickets. The time difference in accessing the memory has the same algorithm complexity. Therefore, the algorithm that was previously limited to the CPU needs to be adjusted to Memory-bound algorithms. The results show that the application of memory-bound proof-of-work algorithm in the ticket purchasing market can better balance the difficulty of buying tickets and resist external attacks, so as to satisfy most people's ticket requirements and ease the pressure of Spring Festival travel.
{"title":"Ticket Market Design Based on Permissionless Blockchain","authors":"Nana Hao","doi":"10.1109/CIRSYSSIM.2018.8525886","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525886","url":null,"abstract":"Proof-of-work, as the core technology of public blockchain, requires users to pay a certain amount of work in order to create new blocks by competition. This article innovatively applies it to the train ticket market, and introduces such a mechanism at the interface of the ticketing system to prevent the system from being attacked. Based on the background of China's internet train ticketing system, this paper analyzes the internal and external attacks on the system, designs an algorithm based on proof-of-work, and expands according to the geographical location, credit rating, and system load based on different problems. However, there is a big difference in CPU performance between different computer devices, leading to the difficulty for some users with insufficient computing power to buy tickets. The time difference in accessing the memory has the same algorithm complexity. Therefore, the algorithm that was previously limited to the CPU needs to be adjusted to Memory-bound algorithms. The results show that the application of memory-bound proof-of-work algorithm in the ticket purchasing market can better balance the difficulty of buying tickets and resist external attacks, so as to satisfy most people's ticket requirements and ease the pressure of Spring Festival travel.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114443393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525875
Mei Bo, Ge Yong, Sun Yi, Z. Hongwei, Zhao Xing, Li Bo, Liu Mengxin
Single Event Upsets in 28nm UTBB-FDSOI SRAM with several types of radiation hardened Bit-cells are studied by heavy ion irradiation test and TCAD simulation. Heavy-ion SEU cross section of the FDSOI SRAM cell are two decades lower than an equivalent cell in planar bulk technology as reported. Through the hardened design, the 8T bit-cells SRAM is able to reach the upset-immune for low LET heavy ions.
{"title":"Study of SEU of 28nm UTBB-FDSOI Device by Heavy Ions and TCAD Simulation","authors":"Mei Bo, Ge Yong, Sun Yi, Z. Hongwei, Zhao Xing, Li Bo, Liu Mengxin","doi":"10.1109/CIRSYSSIM.2018.8525875","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525875","url":null,"abstract":"Single Event Upsets in 28nm UTBB-FDSOI SRAM with several types of radiation hardened Bit-cells are studied by heavy ion irradiation test and TCAD simulation. Heavy-ion SEU cross section of the FDSOI SRAM cell are two decades lower than an equivalent cell in planar bulk technology as reported. Through the hardened design, the 8T bit-cells SRAM is able to reach the upset-immune for low LET heavy ions.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128537553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525888
Zhu Ming, Wang Tong, Gu Hantian, Qu Ruoyuan, Zhu Hengjing, Z. Wei, Tang Min
In this paper, we demonstrate the feasibility and necessity of 3D numerical simulation in the quantitative study of burn-out and latch-up effects in VDMOS and LDMOS power transistors. Insight of which lead to a novel LDMOS layout that is immune to SEL proposed in this paper.
{"title":"Single-Event Effects in Power MOSFETs: Physical Mechanism and Hardening through 3D Simulations","authors":"Zhu Ming, Wang Tong, Gu Hantian, Qu Ruoyuan, Zhu Hengjing, Z. Wei, Tang Min","doi":"10.1109/CIRSYSSIM.2018.8525888","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525888","url":null,"abstract":"In this paper, we demonstrate the feasibility and necessity of 3D numerical simulation in the quantitative study of burn-out and latch-up effects in VDMOS and LDMOS power transistors. Insight of which lead to a novel LDMOS layout that is immune to SEL proposed in this paper.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122109401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525995
Xiaoming Zhu, Baisen Liu, Xiaoguang Wang
High dielectric constant silicon is used as substrate to design new style MEMS antenna in this paper. The design method of silicon antenna with back cavity is proposed. The back rectangular cavity is etched to form hybrid structure of silicon and air, which can lower effective dielectric constant and reduce surface wave loss of silicon substrate. The MEMS processing steps are designed to fabricate MEMS antenna with photoetching and ICP cavity etching process. The simulated and measured results show the compact MEMS antenna has ultra-wide frequency bandwidth and good omni-direction radiation performance.
{"title":"Compact RF MEMS Antenna with Silicon Substrate","authors":"Xiaoming Zhu, Baisen Liu, Xiaoguang Wang","doi":"10.1109/CIRSYSSIM.2018.8525995","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525995","url":null,"abstract":"High dielectric constant silicon is used as substrate to design new style MEMS antenna in this paper. The design method of silicon antenna with back cavity is proposed. The back rectangular cavity is etched to form hybrid structure of silicon and air, which can lower effective dielectric constant and reduce surface wave loss of silicon substrate. The MEMS processing steps are designed to fabricate MEMS antenna with photoetching and ICP cavity etching process. The simulated and measured results show the compact MEMS antenna has ultra-wide frequency bandwidth and good omni-direction radiation performance.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115990373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525907
Tian Xi, Yishan Liu, Xianyue Pan, Wentao Chen
Intra-pulse features extraction of radar is of great research significance in electronic reconnaissance technology. With continuous development and equipment of the new system radar, the characteristics of the modern electromagnetic environment could be summarized as density, complexity and variability, which make the traditional signal identification methods difficult to achieve the desired effect. Therefore, this paper is devoted to the study the methods and performance analysis in extracting intra-pulse features of radar emitters in complex electromagnetic environment, especially in low SNR environment. The final recognition effect exceeded 0db SNR.
{"title":"Intra-pulse Intentional Modulation Recognition of Radar Signals at Low SNR","authors":"Tian Xi, Yishan Liu, Xianyue Pan, Wentao Chen","doi":"10.1109/CIRSYSSIM.2018.8525907","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525907","url":null,"abstract":"Intra-pulse features extraction of radar is of great research significance in electronic reconnaissance technology. With continuous development and equipment of the new system radar, the characteristics of the modern electromagnetic environment could be summarized as density, complexity and variability, which make the traditional signal identification methods difficult to achieve the desired effect. Therefore, this paper is devoted to the study the methods and performance analysis in extracting intra-pulse features of radar emitters in complex electromagnetic environment, especially in low SNR environment. The final recognition effect exceeded 0db SNR.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133527415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525917
Weifeng Zhang, Yan Chen, Jian Wang
In this paper, a novel control strategy using the line voltage information to realize the space vector pulse width modulation (SVPWM) is proposed. The principles and implementation steps of SVPWM are given. In the algorithm flow, the phase angle $boldsymbol{theta}$ of phase voltage is the most important input information for SVPWM strategy. For the three phase system, the phase angle $boldsymbol{theta}$ can't be detected directly. This paper shows the derivation process of line voltage to phase voltage for the three phase three wire system. According to the intrinsic relationship of the line voltage and the phase voltage, the three phase three wire inverter prototype is produced to validate the SVPWM control strategy. It makes the three phase system use the SVPWM reliably and easily. The experimental results are shown. It validate the new control strategy using the line voltage information to realize the SVPWM.
{"title":"A Novel Engineering Implementation of SVPWM Based on Line Voltage Information","authors":"Weifeng Zhang, Yan Chen, Jian Wang","doi":"10.1109/CIRSYSSIM.2018.8525917","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525917","url":null,"abstract":"In this paper, a novel control strategy using the line voltage information to realize the space vector pulse width modulation (SVPWM) is proposed. The principles and implementation steps of SVPWM are given. In the algorithm flow, the phase angle $boldsymbol{theta}$ of phase voltage is the most important input information for SVPWM strategy. For the three phase system, the phase angle $boldsymbol{theta}$ can't be detected directly. This paper shows the derivation process of line voltage to phase voltage for the three phase three wire system. According to the intrinsic relationship of the line voltage and the phase voltage, the three phase three wire inverter prototype is produced to validate the SVPWM control strategy. It makes the three phase system use the SVPWM reliably and easily. The experimental results are shown. It validate the new control strategy using the line voltage information to realize the SVPWM.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116881008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525890
Ruoyuan Qu, Wei Zhang, Qianqian Lv, Ming Tang
A structure of an operational amplifier for neural processing chip is presented in this paper. Due to the special application, noise and power consumption optimization method is introduced from structure level to device level. For structure level, the capacitance proportional circuit is carefully designed to achieve a closed-loop gain and band-pass filtering function at the same time. The adoption of Sub-threshold MOSFETs obtains low noise and high resistance in device level. Fabricated in SMIC 180nm CMOS process, the amplifier yielded a mid-band gain of 57dB and a −3dB bandwidth from 9.2Hz to 80k Hz and input referred noise of 3.06uV while power consumption of 144uW.
{"title":"A Front-End Amplifier for Neural Signal Acquisition","authors":"Ruoyuan Qu, Wei Zhang, Qianqian Lv, Ming Tang","doi":"10.1109/CIRSYSSIM.2018.8525890","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525890","url":null,"abstract":"A structure of an operational amplifier for neural processing chip is presented in this paper. Due to the special application, noise and power consumption optimization method is introduced from structure level to device level. For structure level, the capacitance proportional circuit is carefully designed to achieve a closed-loop gain and band-pass filtering function at the same time. The adoption of Sub-threshold MOSFETs obtains low noise and high resistance in device level. Fabricated in SMIC 180nm CMOS process, the amplifier yielded a mid-band gain of 57dB and a −3dB bandwidth from 9.2Hz to 80k Hz and input referred noise of 3.06uV while power consumption of 144uW.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525981
Pengfei Qian, Lufeng Qiao, Qinghua Chen, Xu Huang
Traditional ways to manage the multicast queues in the queue manager are simple and easy to implement, but with the development of the Internet, the demand for the bandwidth increases rapidly and the problem of these schemes in resources and throughput becomes more serious. In this paper, we analyze three different schemes used for the multicast queues and design a queue manager for CIOQ switches, which can support independent management of multicast queues. The queue manager designed separates unicast queues and multicast queues, thus can provide different QoS (quality of service) for these two queues, and then allocate bandwidth more flexibly. In addition, we use link list instead of independent FIFO in the design in order to save resources. Moreover, the throughput of the system will be improved due to the controlled traffic. The whole design is realized with Verilog HDL, simulated with Modelsim SE 10.2c in Xilinx xc6vlx240t FPGA. The simulation result shows the design can implement the functions we need and useful to meet the requirements of resources, efficiency and throughput, hence the design is valuable.
传统的在队列管理器中管理组播队列的方法简单、易于实现，但随着互联网的发展，对带宽的需求迅速增加，这些方案在资源和吞吐量方面的问题日益严重。本文分析了三种不同的组播队列管理方案，设计了一种用于CIOQ交换机的队列管理器，实现了对组播队列的独立管理。设计的队列管理器将单播队列和组播队列分开，可以为这两个队列提供不同的QoS(服务质量)，从而更灵活地分配带宽。此外，为了节省资源，我们在设计中使用链表而不是独立的FIFO。此外，由于对流量的控制，系统的吞吐量将得到提高。整个设计用Verilog HDL实现，在Xilinx xc6vlx240t FPGA上用Modelsim SE 10.2c进行仿真。仿真结果表明，该设计能够实现我们需要的功能，能够满足资源、效率和吞吐量的要求，具有一定的设计价值。
{"title":"A Queue Manager Support Independent Management of Multicast Queues for CIOQ Switches","authors":"Pengfei Qian, Lufeng Qiao, Qinghua Chen, Xu Huang","doi":"10.1109/CIRSYSSIM.2018.8525981","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525981","url":null,"abstract":"Traditional ways to manage the multicast queues in the queue manager are simple and easy to implement, but with the development of the Internet, the demand for the bandwidth increases rapidly and the problem of these schemes in resources and throughput becomes more serious. In this paper, we analyze three different schemes used for the multicast queues and design a queue manager for CIOQ switches, which can support independent management of multicast queues. The queue manager designed separates unicast queues and multicast queues, thus can provide different QoS (quality of service) for these two queues, and then allocate bandwidth more flexibly. In addition, we use link list instead of independent FIFO in the design in order to save resources. Moreover, the throughput of the system will be improved due to the controlled traffic. The whole design is realized with Verilog HDL, simulated with Modelsim SE 10.2c in Xilinx xc6vlx240t FPGA. The simulation result shows the design can implement the functions we need and useful to meet the requirements of resources, efficiency and throughput, hence the design is valuable.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125952740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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