Fault diagnosis and fault model aliasing

I. Pomeranz, S. Venkataraman, S. Reddy
{"title":"Fault diagnosis and fault model aliasing","authors":"I. Pomeranz, S. Venkataraman, S. Reddy","doi":"10.1109/ISVLSI.2005.34","DOIUrl":null,"url":null,"abstract":"During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit. Equivalence between faults of different models, or a test set that does not distinguish two such faults, can increase the ambiguity as to the defect location as well as its type. We refer to this phenomenon as fault model aliasing. We study the extent to which fault model aliasing can be expected to occur under various test sets. We also describe a test generation procedure that can reduce it.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2005.34","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit. Equivalence between faults of different models, or a test set that does not distinguish two such faults, can increase the ambiguity as to the defect location as well as its type. We refer to this phenomenon as fault model aliasing. We study the extent to which fault model aliasing can be expected to occur under various test sets. We also describe a test generation procedure that can reduce it.
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故障诊断与故障模型混叠
在故障诊断过程中,等效故障的存在,或者应用于电路的测试集无法区分的故障,可能会对缺陷的位置产生模糊。如果在电路的不同位置存在两个故障时,被测电路产生的响应与电路响应相匹配,则会发生这种情况。不同模型的故障之间的等价性,或者一个测试集不能区分两个这样的故障,会增加缺陷位置及其类型的模糊性。我们把这种现象称为故障模型混叠。我们研究了故障模型混叠在不同测试集下可能发生的程度。我们还描述了一个可以减少它的测试生成过程。
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