In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 /spl mu/m CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.
{"title":"High performance array processor for video decoding","authors":"Jooheung Lee, N. Vijaykrishnan, M. J. Irwin","doi":"10.1109/ISVLSI.2005.36","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.36","url":null,"abstract":"In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 /spl mu/m CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121885657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes the design and implementation of an 8 /spl times/8 2D DCT chip for use in low-power applications. The design exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8 /spl times/8 2D DCT @ 50 MHz consuming around 137mW of power.
{"title":"Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]","authors":"Soumik Ghosh, Soujanya Venigalla, M. Bayoumi","doi":"10.1109/ISVLSI.2005.25","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.25","url":null,"abstract":"The paper describes the design and implementation of an 8 /spl times/8 2D DCT chip for use in low-power applications. The design exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8 /spl times/8 2D DCT @ 50 MHz consuming around 137mW of power.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128561702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software-managed memories are important in realtime embedded environments where execution time predictability is an important requirement. With the proliferation of embedded multi-processor systems, software support for their memories is becoming an attractive research area in real-time embedded computing. One of the critical problems in embedded real-time multi-processor SoCs (system-on-a-chip) is to reduce the number of off-chip references. This is because frequent off-chip references can be very costly from both performance and power perspectives. In this paper, we propose a novel compiler-driven strategy for reducing the number of off-chip references, which is based on cooperation between the processors in the multi-processor architecture. Specifically, in the proposed strategy, the processors cache data in their local memories, under compiler control, on behalf of each other if doing so reduces the number of off-chip references.
{"title":"Exploiting inter-processor data sharing for improving behavior of multi-processor SoCs","authors":"Guilin Chen, Guangyu Chen, O. Ozturk, M. Kandemir","doi":"10.1109/ISVLSI.2005.32","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.32","url":null,"abstract":"Software-managed memories are important in realtime embedded environments where execution time predictability is an important requirement. With the proliferation of embedded multi-processor systems, software support for their memories is becoming an attractive research area in real-time embedded computing. One of the critical problems in embedded real-time multi-processor SoCs (system-on-a-chip) is to reduce the number of off-chip references. This is because frequent off-chip references can be very costly from both performance and power perspectives. In this paper, we propose a novel compiler-driven strategy for reducing the number of off-chip references, which is based on cooperation between the processors in the multi-processor architecture. Specifically, in the proposed strategy, the processors cache data in their local memories, under compiler control, on behalf of each other if doing so reduces the number of off-chip references.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129642965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper carries out a comparative study on the methods of dicing multi-project wafers (MPW). Our dicing method results in using 40% fewer wafers both for low and high volume production.
{"title":"A comparative study on dicing of multiple project wafers","authors":"Meng-Chiou Wu, Rung-Bin Lin","doi":"10.1109/ISVLSI.2005.3","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.3","url":null,"abstract":"This paper carries out a comparative study on the methods of dicing multi-project wafers (MPW). Our dicing method results in using 40% fewer wafers both for low and high volume production.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Saputra, O. Ozturk, N. Vijaykrishnan, M. Kandemir, R. Brooks
As embedded systems are being used in a wide variety of critical applications, providing security to data stored and processed in these systems has become an important issue. However, providing security incurs performance and power overheads that need to be limited in resource-constrained embedded environments. Consequently, architectural support to limit these overheads to be incurred only while storing or processing vital data is desirable. In this paper, we present an architecture that provides selective encryption protection for storage and processing protection to power analysis attacks for data marked as requiring security. Further, we show how the code can be transformed to reduce the overhead associated with protecting secure data.
{"title":"A data-driven approach for embedded security","authors":"H. Saputra, O. Ozturk, N. Vijaykrishnan, M. Kandemir, R. Brooks","doi":"10.1109/ISVLSI.2005.4","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.4","url":null,"abstract":"As embedded systems are being used in a wide variety of critical applications, providing security to data stored and processed in these systems has become an important issue. However, providing security incurs performance and power overheads that need to be limited in resource-constrained embedded environments. Consequently, architectural support to limit these overheads to be incurred only while storing or processing vital data is desirable. In this paper, we present an architecture that provides selective encryption protection for storage and processing protection to power analysis attacks for data marked as requiring security. Further, we show how the code can be transformed to reduce the overhead associated with protecting secure data.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Chouliaras, T. Jacobs, A. K. Kumaraswamy, J. Núñez-Yáñez
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder.
{"title":"Configurable multiprocessors for high-performance MPEG-4 video coding","authors":"V. Chouliaras, T. Jacobs, A. K. Kumaraswamy, J. Núñez-Yáñez","doi":"10.1109/ISVLSI.2005.24","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.24","url":null,"abstract":"We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130193779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using the nonlinear feedback shift register in testing is known to create a test set for combinational circuits instead of using the deterministic test set. The nonlinear property of feedback shift register is used differently here to reduce the test data volume for combinational circuits without using the nonlinear feedback shift register. In addition, a dictionary coding method is applied to further decrease a reduced test set. Results with benchmark circuits show a great improvement in the reduction of test data volume.
{"title":"Using the nonlinear property of FSR and dictionary coding for reduction of test volume","authors":"Il-soo Lee, Jae-Hoon Jeong, A. Ambler","doi":"10.1109/ISVLSI.2005.75","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.75","url":null,"abstract":"Using the nonlinear feedback shift register in testing is known to create a test set for combinational circuits instead of using the deterministic test set. The nonlinear property of feedback shift register is used differently here to reduce the test data volume for combinational circuits without using the nonlinear feedback shift register. In addition, a dictionary coding method is applied to further decrease a reduced test set. Results with benchmark circuits show a great improvement in the reduction of test data volume.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115945367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Livingston, H. T. Ngo, Ming Z. Zhang, Li Tao, V. Asari
In this paper, we propose an efficient VLSI architecture for real time enhancement of video containing non-uniform and low light conditions. The nonlinear transfer function is determined by the cumulative distribution function of the previous frame. A dataflow design technique is used to construct a pipelined multimodule architecture. The design is capable of processing 73 1024/spl times/1024 video frames per second.
{"title":"Design of a real time system for nonlinear enhancement of video streams by an integrated neighborhood dependent approach","authors":"A. Livingston, H. T. Ngo, Ming Z. Zhang, Li Tao, V. Asari","doi":"10.1109/ISVLSI.2005.28","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.28","url":null,"abstract":"In this paper, we propose an efficient VLSI architecture for real time enhancement of video containing non-uniform and low light conditions. The nonlinear transfer function is determined by the cumulative distribution function of the previous frame. A dataflow design technique is used to construct a pipelined multimodule architecture. The design is capable of processing 73 1024/spl times/1024 video frames per second.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"34 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Smailagic, D. Siewiorek, Uwe Maurer, Anthony G. Rowe, Karen P. Tang
In this paper, we introduce a novel context sensitive system design paradigm. Multiple sensors/computational architecture, in the form of our eWatch device, is used to infer the activities that the system is encountering, and can provide a platform for context-aware computing. We created an eWatch prototype that senses user activities and notifies them when important messages have arrived. An accelerometer and microphone provide inputs to a model of interruptibility. A vibration motor for tactile feedback and two ultra bright LEDs for visual feedback provide user notification through different vibration patterns and colors. eWatch is transparently integrated into the user's environment, and communicates via Bluetooth. This new class of integrated systems underscores the need for new forms of regularity, constraints, and design structure. Our results indicate the power of our method to accurately determine a meaningful context model while only requiring data from our eWatch device.
{"title":"eWatch: context sensitive system design case study","authors":"A. Smailagic, D. Siewiorek, Uwe Maurer, Anthony G. Rowe, Karen P. Tang","doi":"10.1109/ISVLSI.2005.31","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.31","url":null,"abstract":"In this paper, we introduce a novel context sensitive system design paradigm. Multiple sensors/computational architecture, in the form of our eWatch device, is used to infer the activities that the system is encountering, and can provide a platform for context-aware computing. We created an eWatch prototype that senses user activities and notifies them when important messages have arrived. An accelerometer and microphone provide inputs to a model of interruptibility. A vibration motor for tactile feedback and two ultra bright LEDs for visual feedback provide user notification through different vibration patterns and colors. eWatch is transparently integrated into the user's environment, and communicates via Bluetooth. This new class of integrated systems underscores the need for new forms of regularity, constraints, and design structure. Our results indicate the power of our method to accurately determine a meaningful context model while only requiring data from our eWatch device.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127269172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose boost logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an energy recovering "boost" stage to provide an efficient gate overdrive to a highly voltage-scaled logic at near-threshold supply voltage. We have evaluated our logic family using simulation results from an 8-bit carry-save multiplier in a 0.13 /spl mu/m CMOS process with V/sub th/ = 340 mV at 1.4 GHz and a 1.1 V supply voltage, the boost multiplier dissipates 3.44 pJ per computation, achieving 57% energy savings with respect to its static CMOS counterpart. Using low V/sub th/ devices, boost logic has been verified to operate at 2 GHz with a 1.2 V voltage supply and 3.76 pJ energy dissipation per cycle.
{"title":"Boost logic : a high speed energy recovery circuit family","authors":"V. Sathe, M. Papaefthymiou, C. Ziesler","doi":"10.1109/ISVLSI.2005.22","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.22","url":null,"abstract":"In this paper, we propose boost logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an energy recovering \"boost\" stage to provide an efficient gate overdrive to a highly voltage-scaled logic at near-threshold supply voltage. We have evaluated our logic family using simulation results from an 8-bit carry-save multiplier in a 0.13 /spl mu/m CMOS process with V/sub th/ = 340 mV at 1.4 GHz and a 1.1 V supply voltage, the boost multiplier dissipates 3.44 pJ per computation, achieving 57% energy savings with respect to its static CMOS counterpart. Using low V/sub th/ devices, boost logic has been verified to operate at 2 GHz with a 1.2 V voltage supply and 3.76 pJ energy dissipation per cycle.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"2021 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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