Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs

Abstract

In this paper, in order to evaluate the higher hole mobility of the [110]-surface devices against that of the [100]-surface MOSFETs, we have studied the [110]-surface hole mobility behaviors of thin film (TF) strained-SOI, unstrained-SOI, and unstrained-bulk MOSFETs in detail, as functions of E/sub eff/, current flow direction, and temperature. We have introduced a model for [110]-surface hole mobility. We discuss the V/sub th/ control of the strained-SOIs by applying the back-gate bias under the buried oxide without controlling the channel dopant, as well as the transconductance enhancement down to the quarter-micron region. A device design concept for strained-CMOS is proposed to optimize the channel surface orientation and the drain current flow direction of n- and p-MOSFETs.