Power aware minimization of complementary logic functions based on maximal HD

Abstract

In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where n represents the support of a Boolean function. The quality of the resulting circuits, evaluated on the basis of established cost metrics for a modest 0.35mu TSMC CMOS process, demonstrate average savings in power by 14.39% for the samples mentioned in this paper, besides reduction in gate and literal count by 36.59% and 11.35% respectively, over the best of existing methods