Eutectic solder flip chip technology for chip scale package

C. Takubo, N. Hirano, K. Doi, H. Tazawa, E. Hosomi, Y. Hiruta
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引用次数: 7

Abstract

Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the electrodes, a strong self-alignment effect and a low melting point. So, it is quite suitable for a chip assembly onto the plastic substrate as well as the ceramic substrate. An electroplating method has been developed for the formation of the eutectic solder bumps. The barrier metals has been selected as Ti/Ni/Pd for higher barrier effect. The flip chip interconnection process has been also developed. The various kinds of the reliability of the interconnection portion were investigated using the test vehicle of the ceramic and plastic substrate. The results of the test confirmed the reliable fabrication of the CSP using the eutectic solder flip chip technology.
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芯片级封装用共晶焊料倒装技术
芯片级封装(CSP)是采用带共晶锡/铅凸点的倒装芯片技术开发的。封装尺寸仅比芯片尺寸大1毫米。共晶焊料对电极的润湿性好,自对准效果强,熔点低。因此,它非常适合在塑料基板上以及陶瓷基板上进行芯片组装。提出了一种形成共晶凸点的电镀方法。阻挡金属选择Ti/Ni/Pd具有较高的阻挡效果。倒装芯片互连工艺也得到了发展。利用陶瓷基板和塑料基板的试验车,对互连部分的各种可靠性进行了研究。测试结果证实了采用共晶焊料倒装芯片技术制造CSP的可靠性。
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Statistical optimization of high frequency LDMOS devices via hyper-fractionated experimental designs High temperature deformation of high density interconnects and packages by moire interferometry/FEM hybrid method Microsystems for medical applications The manufacturing logistics of cofire ceramic electronic packages Eutectic solder flip chip technology for chip scale package
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