Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559750
T. Carr
The manufacturing cycletime of cofire ceramic Pin Grid Array (PGA) electronic packages has been modeled using the principles of chemical kinetics. In this paper, the rates and mechanisms of chemical reactions are discussed in relation to the manufacturing cycletime. Alcoa Electronic Packaging has used this methodology to achieve world class status in the manufacturing of Pin Grid Array electronic packages.
{"title":"The manufacturing logistics of cofire ceramic electronic packages","authors":"T. Carr","doi":"10.1109/IEMT.1996.559750","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559750","url":null,"abstract":"The manufacturing cycletime of cofire ceramic Pin Grid Array (PGA) electronic packages has been modeled using the principles of chemical kinetics. In this paper, the rates and mechanisms of chemical reactions are discussed in relation to the manufacturing cycletime. Alcoa Electronic Packaging has used this methodology to achieve world class status in the manufacturing of Pin Grid Array electronic packages.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115102422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559778
A. Donnell, S. Singhal
Process Quality is one of the key factors and early indicators that impacts outgoing duality and removal rates of the product (system or component). During the last five years, Lucent Technologies in Dallas (formerly AT&T Power Systems) has placed great emphasis on improving process quality by properly implementing Statistical Process Control (SPC). In 1990, AT&T Power Systems started their journey of implementing Total Quality Management (TQM) and challenging for the most prestigious duality award, the Deming Prize. A robust SPC program is a key requirement of the Deming Prize. As a result of the successful implementation of TQM and SPC, AT&T Power Systems was the first United States manufacturing company (and the second US company) to win the Deming Prize. During the examination process for the Deming Prize, an intense emphasis is placed on auditing the systems and processes in place to improve the product quality. Specifically, the effective implementation of SPC is a fundamental element of the examination process. SPC implementation included: a well structured and documented SPC plan; a comprehensive SPC training program for engineers, managers, and production employees; a team approach; and senior management involvement and reviews. The key elements of the SPC Plan are: product/process quality metrics, process control, process improvement, and capability indices improvement. This paper presents the details of this plan and resulting improvements in the product quality. The SPC implementation and product quality improvement exceeded the expectations of the JUSE (Japanese Union of Scientist and Engineers) examiners. Currently, Lucent Technologies (formerly AT&T Power Systems) is viewed as a world leader in quality and TQM.
过程质量是影响产品(系统或组件)输出对偶性和去除率的关键因素和早期指标之一。在过去的五年中，位于达拉斯的朗讯技术公司(前身为AT&T Power Systems)非常重视通过正确实施统计过程控制(SPC)来提高过程质量。1990年，AT&T电力系统开始了他们实施全面质量管理(TQM)的旅程，并向最负盛名的双重性奖戴明奖发起挑战。一个强大的SPC程序是戴明奖的关键要求。由于TQM和SPC的成功实施，AT&T电力系统是第一家美国制造公司(也是第二家美国公司)赢得戴明奖。在戴明奖的审查过程中，重点是审查现有的系统和流程，以提高产品质量。具体来说，SPC的有效实施是审查过程的基本要素。SPC实施包括:一个结构良好、文件化的SPC计划;针对工程师、经理和生产员工的全面SPC培训计划;团队方法;高级管理层的参与和审查。SPC计划的关键要素是:产品/过程质量度量、过程控制、过程改进和能力指标改进。本文介绍了该计划的细节以及由此带来的产品质量的改进。SPC的实施和产品质量的改进超出了JUSE(日本科学家和工程师联盟)审查员的预期。目前，朗讯科技(前身为AT&T电力系统)被视为质量和全面质量管理的全球领导者。
{"title":"SPC implementation for improving product quality","authors":"A. Donnell, S. Singhal","doi":"10.1109/IEMT.1996.559778","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559778","url":null,"abstract":"Process Quality is one of the key factors and early indicators that impacts outgoing duality and removal rates of the product (system or component). During the last five years, Lucent Technologies in Dallas (formerly AT&T Power Systems) has placed great emphasis on improving process quality by properly implementing Statistical Process Control (SPC). In 1990, AT&T Power Systems started their journey of implementing Total Quality Management (TQM) and challenging for the most prestigious duality award, the Deming Prize. A robust SPC program is a key requirement of the Deming Prize. As a result of the successful implementation of TQM and SPC, AT&T Power Systems was the first United States manufacturing company (and the second US company) to win the Deming Prize. During the examination process for the Deming Prize, an intense emphasis is placed on auditing the systems and processes in place to improve the product quality. Specifically, the effective implementation of SPC is a fundamental element of the examination process. SPC implementation included: a well structured and documented SPC plan; a comprehensive SPC training program for engineers, managers, and production employees; a team approach; and senior management involvement and reviews. The key elements of the SPC Plan are: product/process quality metrics, process control, process improvement, and capability indices improvement. This paper presents the details of this plan and resulting improvements in the product quality. The SPC implementation and product quality improvement exceeded the expectations of the JUSE (Japanese Union of Scientist and Engineers) examiners. Currently, Lucent Technologies (formerly AT&T Power Systems) is viewed as a world leader in quality and TQM.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122400049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559747
H. Kergel, B. Monno
During the production of high-value electronic boards it is often necessary to exchange BGAs within a repair process. The repair process generally is a manual process where the use of hot gas is common. FINETECH electronic GmbH of Berlin/Germany is developing and producing equipment for the assembly and the rework of PC-boards populated with high sophisticated ICs as well as flip chip devices. This equipment has to meet various requirements which is realized by having a modular concept. The base of the workstations is a patented vision alignment and placement principle which offers many advantages. Additionally, a new method to control the temperature of the hot gas was developed and introduced. Here the main patented idea is to control the temperature of the gas by mixing a hot and a cold gas stream instead of controlling the electrical power of a heating element for one single gas stream. Another key issue for a successful repair process is the design of the nozzles for the soldering and desoldering of the BGAs. All actual parameters of a specific repair or soldering cycle have to be protocolled and saved in order to reproduce each cycle at any time. Therefore, the human factor within a manual process is being suppressed to a minimum.
{"title":"Equipment requirements for the repair of BGA-boards","authors":"H. Kergel, B. Monno","doi":"10.1109/IEMT.1996.559747","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559747","url":null,"abstract":"During the production of high-value electronic boards it is often necessary to exchange BGAs within a repair process. The repair process generally is a manual process where the use of hot gas is common. FINETECH electronic GmbH of Berlin/Germany is developing and producing equipment for the assembly and the rework of PC-boards populated with high sophisticated ICs as well as flip chip devices. This equipment has to meet various requirements which is realized by having a modular concept. The base of the workstations is a patented vision alignment and placement principle which offers many advantages. Additionally, a new method to control the temperature of the hot gas was developed and introduced. Here the main patented idea is to control the temperature of the gas by mixing a hot and a cold gas stream instead of controlling the electrical power of a heating element for one single gas stream. Another key issue for a successful repair process is the design of the nozzles for the soldering and desoldering of the BGAs. All actual parameters of a specific repair or soldering cycle have to be protocolled and saved in order to reproduce each cycle at any time. Therefore, the human factor within a manual process is being suppressed to a minimum.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122986513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559717
M. Itagaki, Y. Bessho, K. Eda, T. Ishida
A zero X-Y shrinkage low temperature cofired ceramic (LTCC) substrate was developed, that was applied to the flip-chip bonded chip-size-packages (CSPs) and multi-chip modules (MCMs). The Ag internal conductor,the AgPd external conductor and the newly developed Ag via conductor could be used by matching the sintering shrinkage behavior with that of the zero X-Y shrinkage LTCC substrate. The flip-chip bonding using stud-bump-bonding (SBB) technique could be performed onto the external conductor of this developed substrate without Au plating and stable flip-chip bendability was obtained.
{"title":"A zero X-Y shrinkage low temperature cofired ceramic substrate using Ag and AgPd conductors for flip-chip bonding","authors":"M. Itagaki, Y. Bessho, K. Eda, T. Ishida","doi":"10.1109/IEMT.1996.559717","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559717","url":null,"abstract":"A zero X-Y shrinkage low temperature cofired ceramic (LTCC) substrate was developed, that was applied to the flip-chip bonded chip-size-packages (CSPs) and multi-chip modules (MCMs). The Ag internal conductor,the AgPd external conductor and the newly developed Ag via conductor could be used by matching the sintering shrinkage behavior with that of the zero X-Y shrinkage LTCC substrate. The flip-chip bonding using stud-bump-bonding (SBB) technique could be performed onto the external conductor of this developed substrate without Au plating and stable flip-chip bendability was obtained.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129820934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559674
D. Gamota, Cindy M. Melton
Encapsulant materials for flip chip on board assemblies (FCOB) were developed to address the issues observed during assembly of consumer electronic products on a high volume manufacturing FCOB/SMT line. The development of encapsulant materials with enhanced flow properties and faster curing kinetics is critical to continue the move towards the integration of FCOB assemblies as an alternative packaging system in electronic products. The results from this study showed that materials with enhanced flow properties were developed and some approached a 10/spl times/ reduction in the time to underfill a flip chip when compared to the qualified encapsulant system. The viscosity, surface tension, and filler particle sizes were studied in an attempt to correlate these properties to the recorded underfill times. Materials characterization studies were performed to determine the glass transition temperatures (Tg), tensile elastic and loss moduli (E' and E"), flow profiles, coefficients of thermal expansion (CTE), and apparent strengths of adhesion. In addition, reliability tests were conducted using FR4 substrates to determine the relationship between materials properties and reliability responses. The experimental results suggested that there is a strong potential to develop materials for FCOB assemblies with enhanced flow properties and shorter cure schedules without compromising reliability behavior. In addition, unique encapsulant materials systems with sufficient fluxing activities to remove the metal oxides on the die and/or substrate bumps and assist in the formation of metallurgical interconnects were developed: reflowable encapsulants. The experimental process flow was as follows, a finite volume of reflowable encapsulant was dispensed on the PCB at the die site, the die was aligned over the bond pads, and the die was placed into the encapsulant. Next, the FCOB assembly was transferred to a reflow furnace and subjected to a standard SMT eutectic Pb/Sn reflow profile, the solder was reflowed, interconnects were formed between the die and PCB, and the reflowable encapsulant was partially cured. Promising reliability results were obtained warranting further evaluation of the reflowable materials systems and process.
{"title":"Advanced encapsulant materials systems for flip-chip-on-board assemblies. I. Encapsulant materials with improved manufacturing properties. II. Materials to integrate the reflow and underfilling processes","authors":"D. Gamota, Cindy M. Melton","doi":"10.1109/IEMT.1996.559674","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559674","url":null,"abstract":"Encapsulant materials for flip chip on board assemblies (FCOB) were developed to address the issues observed during assembly of consumer electronic products on a high volume manufacturing FCOB/SMT line. The development of encapsulant materials with enhanced flow properties and faster curing kinetics is critical to continue the move towards the integration of FCOB assemblies as an alternative packaging system in electronic products. The results from this study showed that materials with enhanced flow properties were developed and some approached a 10/spl times/ reduction in the time to underfill a flip chip when compared to the qualified encapsulant system. The viscosity, surface tension, and filler particle sizes were studied in an attempt to correlate these properties to the recorded underfill times. Materials characterization studies were performed to determine the glass transition temperatures (Tg), tensile elastic and loss moduli (E' and E\"), flow profiles, coefficients of thermal expansion (CTE), and apparent strengths of adhesion. In addition, reliability tests were conducted using FR4 substrates to determine the relationship between materials properties and reliability responses. The experimental results suggested that there is a strong potential to develop materials for FCOB assemblies with enhanced flow properties and shorter cure schedules without compromising reliability behavior. In addition, unique encapsulant materials systems with sufficient fluxing activities to remove the metal oxides on the die and/or substrate bumps and assist in the formation of metallurgical interconnects were developed: reflowable encapsulants. The experimental process flow was as follows, a finite volume of reflowable encapsulant was dispensed on the PCB at the die site, the die was aligned over the bond pads, and the die was placed into the encapsulant. Next, the FCOB assembly was transferred to a reflow furnace and subjected to a standard SMT eutectic Pb/Sn reflow profile, the solder was reflowed, interconnects were formed between the die and PCB, and the reflowable encapsulant was partially cured. Promising reliability results were obtained warranting further evaluation of the reflowable materials systems and process.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124652047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559686
Jiansen Zhu, D. Zou, F. Dai, Sheng Liu, Yi Guo
In the current study, 1200 I/mm grating or 600 1/mm gratings are replicated at either 80/spl deg/C or 160/spl deg/C onto the cross sections of several high density area interconnects and packages. These packages include BGA, flip-chip, and glob-top packages. The specimens are measured at room temperature for the thermal deformation induced by the cooling process. The strain distributions inside the solder joints are analyzed by both the moire interferometry and experimental/FEM hybrid method. Warpage of the packaging systems was measured and the effects of the bonding, encapsulation, soldering, and geometry on the deformation are discussed.
{"title":"High temperature deformation of high density interconnects and packages by moire interferometry/FEM hybrid method","authors":"Jiansen Zhu, D. Zou, F. Dai, Sheng Liu, Yi Guo","doi":"10.1109/IEMT.1996.559686","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559686","url":null,"abstract":"In the current study, 1200 I/mm grating or 600 1/mm gratings are replicated at either 80/spl deg/C or 160/spl deg/C onto the cross sections of several high density area interconnects and packages. These packages include BGA, flip-chip, and glob-top packages. The specimens are measured at room temperature for the thermal deformation induced by the cooling process. The strain distributions inside the solder joints are analyzed by both the moire interferometry and experimental/FEM hybrid method. Warpage of the packaging systems was measured and the effects of the bonding, encapsulation, soldering, and geometry on the deformation are discussed.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559746
G. Grossmann, L. Weber, K. Heiduschke
The occurrence of new packages as well as the ongoing miniaturisation in SMT make the evaluation of the reliability of solder joints an permanent task. Accelerated testing, especially passive thermal cycling, is a important tool to evaluate the lifetime of solder joints. However, tin-lead solder behaves viscoplastically even at ambient temperature because of its low melting point and therefore the temperatures of the tests performed as well as the temperature change rate are very important parameters for testing. Different deformation rates cause different deformation mechanisms to occur. Therefore it is mandatory to take the metallurgical behaviour of tin-lead solder into account when accelerated tests are to be performed. However, many accelerated test performed in industry do not at all care for this fact: Temperature shock chambers are used in order to shorten the test time activating deformation mechanisms that do not occur in reality. Test chambers are overloaded, test specimen with high mass are tested or the specimen are placed with varying orientations to the air stream of the chamber not caring, which temperatures and temperature exchange rates occur in the solder joints.
{"title":"Metallurgical considerations for accelerated testing of soft solder joints","authors":"G. Grossmann, L. Weber, K. Heiduschke","doi":"10.1109/IEMT.1996.559746","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559746","url":null,"abstract":"The occurrence of new packages as well as the ongoing miniaturisation in SMT make the evaluation of the reliability of solder joints an permanent task. Accelerated testing, especially passive thermal cycling, is a important tool to evaluate the lifetime of solder joints. However, tin-lead solder behaves viscoplastically even at ambient temperature because of its low melting point and therefore the temperatures of the tests performed as well as the temperature change rate are very important parameters for testing. Different deformation rates cause different deformation mechanisms to occur. Therefore it is mandatory to take the metallurgical behaviour of tin-lead solder into account when accelerated tests are to be performed. However, many accelerated test performed in industry do not at all care for this fact: Temperature shock chambers are used in order to shorten the test time activating deformation mechanisms that do not occur in reality. Test chambers are overloaded, test specimen with high mass are tested or the specimen are placed with varying orientations to the air stream of the chamber not caring, which temperatures and temperature exchange rates occur in the solder joints.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"37 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132130493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559792
T. Carmon-Freed
The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned.
{"title":"Scheduling semiconductor device test operations","authors":"T. Carmon-Freed","doi":"10.1109/IEMT.1996.559792","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559792","url":null,"abstract":"The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131168041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559737
D. Dance, A. Veltri, W. Lashbrook
Activities driven by ESH concerns can significantly impact electronics manufacturing costs. The inability to account for ESH costs and link them to designs and processes forces many in the industry to make critical business and operational decisions with an incomplete understanding of their ESH economic impact. ESH cost modeling is a tool for use by ESH and engineering during concurrent design activities to evaluate the ESH impacts of product or process design options. A joint research and development project involving, Oregon State University, Wright Williams and Kelly, and SEMATECH is extending cost of ownership (COO) for analysis of ESH cost drivers. COO is a tool for evaluating the ESH impacts of process equipment. The ESH COO model provides a framework for accounting activities that drive ESH costs at the manufacturing process level. Activity-based cost analysis and life-cycle analysis are important parts of this ESH cost modeling framework. Decision analysis, based on analyzing ESH data and costs using standard software algorithms and equations, allows the electronics industry to remain competitive while cost-effectively meeting ESH requirements. Improved ESH accounting and decision support tools like COO allow the ESH operating staff and management to better manage ESH, costs and impacts. These tools provide improved long-term financial and ESH performance.
由ESH关注驱动的活动可以显著影响电子产品的制造成本。由于无法考虑ESH成本并将其与设计和流程联系起来，许多业内人士在做出关键业务和运营决策时，对其ESH经济影响的理解并不完整。ESH成本建模是ESH和工程在并行设计活动中使用的工具，用于评估产品或工艺设计选项对ESH的影响。俄勒冈州立大学(Oregon State University)、Wright Williams和Kelly以及SEMATECH正在开展一项联合研发项目，旨在扩展拥有成本(COO)，以分析ESH成本驱动因素。COO是评价工艺设备的ESH影响的工具。ESH COO模型为在制造过程级别驱动ESH成本的会计活动提供了一个框架。基于作业的成本分析和生命周期分析是ESH成本建模框架的重要组成部分。决策分析，基于使用标准软件算法和方程分析ESH数据和成本，使电子行业保持竞争力，同时经济有效地满足ESH要求。改进的ESH会计和决策支持工具(如COO)使ESH运营人员和管理层能够更好地管理ESH、成本和影响。这些工具提供了改善的长期财务和ESH绩效。
{"title":"Applications of cost of ownership to environment, safety and health","authors":"D. Dance, A. Veltri, W. Lashbrook","doi":"10.1109/IEMT.1996.559737","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559737","url":null,"abstract":"Activities driven by ESH concerns can significantly impact electronics manufacturing costs. The inability to account for ESH costs and link them to designs and processes forces many in the industry to make critical business and operational decisions with an incomplete understanding of their ESH economic impact. ESH cost modeling is a tool for use by ESH and engineering during concurrent design activities to evaluate the ESH impacts of product or process design options. A joint research and development project involving, Oregon State University, Wright Williams and Kelly, and SEMATECH is extending cost of ownership (COO) for analysis of ESH cost drivers. COO is a tool for evaluating the ESH impacts of process equipment. The ESH COO model provides a framework for accounting activities that drive ESH costs at the manufacturing process level. Activity-based cost analysis and life-cycle analysis are important parts of this ESH cost modeling framework. Decision analysis, based on analyzing ESH data and costs using standard software algorithms and equations, allows the electronics industry to remain competitive while cost-effectively meeting ESH requirements. Improved ESH accounting and decision support tools like COO allow the ESH operating staff and management to better manage ESH, costs and impacts. These tools provide improved long-term financial and ESH performance.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-14DOI: 10.1109/IEMT.1996.559791
J.M. Czarnowski, M. Reynolds, M.T. Hayes, C. Ellis, R.W. Johnson, M. Palmer
The new technologies of flip chip, DCA, and CSP require conversion from perimeter bond pads to total area bonded dies. To fill this need, new low-cost area bonding conductive (ABC) adhesives have been developed under an ARPA TRP grant. An ABC adhesive is a two region thermoset adhesive with electrically conductive epoxy adhesive pads surrounded by a continuous oxide filled dielectric adhesive to form a total area bond. Both regions are solvent free, B-staged, non tacky epoxies supplied on a Mylar carrier release film, which cure, with no volatiles or outgassing to yield high Tg, high strength adhesive bonds. In contrast to previous random particle Z-axis adhesives, the ABC adhesives have conductive areas only at the bond pad locations. Area bond test die, designed and fabricated by the Auburn University Microelectronics Center have been successfully bonded to FR4, flex, and thin film ceramic substrates. Test die features include four point Kelvin contact strings and interdigitated daisy chains on 10 mil and 20 mil pitch. Various surface metallizations have been explored and evaluated. Cure times and temperatures are being optimized. This paper will discuss design and fabrication of the test die, including surface metallization and the problems encountered therein. It will describe the process and its optimization.
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