A 10-b 30-MS/s 3.4-mW pipelined ADC with 2.0-Vpp full-swing input at a 1.0-V supply

Abstract

This paper describes a low-voltage design for a pipelined A/D converter that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output range of all MDACs by 50% compared with the ADCpsilas input. We designed a 10-b pipelined ADC with the proposed 2b-MDAC. The fabricated ADC using a 90-nm CMOS process is able to operate in 2.0-Vpp full-swing input at a 1.0-V supply in spite of it using conventional op-amps, and has SNDR/SFDR of 57.5 dB/69.0 dB at 30 MS/s with only 3.4 mW.