2D Analytical calculation of the source/drain access resistance in DG-MOSFET structures

Abstract

Since DG-MOSFETs reached channel length down to 20nm, the parasitic source/drain resistances get more important and can't be neglected. To calculate these resistances in such devices a two-dimensional model in analytical closed-form has been derived by using the conformal mapping technique. Additionally, the model is able to predict the parasitic resistances for DG-MOSFETs with raised source drain (RSD) structures and/or wrapped contacts. The influence of source/drain geometries on access resistances is accurately described and a bias dependency is obtained by introducing two fitting parameters. The model is compared with the parasitic source/drain resistances determined from TCAD device simulations.