Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757988
M. Berthomé, S. Barraud, A. Ionescu, T. Ernst
In this paper we propose a new physically-based analytical model for junctionless transistors. Various MOSFET architectures based on single-gate (SG), double-gate (DG) and Gate-All-Around (GAA) transistors are studied. In particular the trade-off between the electrostatic control and the current drivability (first-order evaluation) is evaluated. Comparisons between numerical and analytical results are done in order to verify assumptions for pinch-off voltage and depletion regions. Traditional analytical expressions for this phenomenon are re-explored, and used to derive some technological guidelines.
{"title":"Physically-based, multi-architecture, analytical model for junctionless transistors","authors":"M. Berthomé, S. Barraud, A. Ionescu, T. Ernst","doi":"10.1109/ULIS.2011.5757988","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757988","url":null,"abstract":"In this paper we propose a new physically-based analytical model for junctionless transistors. Various MOSFET architectures based on single-gate (SG), double-gate (DG) and Gate-All-Around (GAA) transistors are studied. In particular the trade-off between the electrostatic control and the current drivability (first-order evaluation) is evaluated. Comparisons between numerical and analytical results are done in order to verify assumptions for pinch-off voltage and depletion regions. Traditional analytical expressions for this phenomenon are re-explored, and used to derive some technological guidelines.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127476005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757959
J. Nishimura, T. Saraya, T. Hiramoto
Random telegraph noise (RTN) in bulk and fully depleted (FD) SOI MOSFETs are measured by device matrix array (DMA) TEG for statistical analysis. It is found that, in the tail part of the distribution, threshold voltage change by RTN (ΔVth) in FD SOI MOSFETs is smaller than that in Bulk MOSFETs. 3D device simulation confirms that ΔVth becomes very large in bulk MOSFETs when a trap happens to be in the valley of channel potential caused by random dopant fluctuation (RDF), while the possibility of large ΔVth is small in FD SOI MOSFETs because the channel potential profile is smooth due to low impurity density.
采用器件矩阵阵列(DMA) TEG测量了散装和完全耗尽(FD) SOI mosfet的随机电报噪声(RTN)，并进行了统计分析。研究发现，在分布的尾部，RTN (ΔVth)在FD SOI mosfet中的阈值电压变化小于Bulk mosfet。三维器件模拟证实，当陷阱恰好处于随机掺杂波动(RDF)引起的沟道电位谷时，块体mosfet中ΔVth会变得非常大，而FD SOI mosfet中ΔVth变大的可能性很小，因为低杂质密度使得沟道电位曲线平滑。
{"title":"Statistical comparison of random telegraph noise (RTN) in bulk and fully depleted SOI MOSFETs","authors":"J. Nishimura, T. Saraya, T. Hiramoto","doi":"10.1109/ULIS.2011.5757959","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757959","url":null,"abstract":"Random telegraph noise (RTN) in bulk and fully depleted (FD) SOI MOSFETs are measured by device matrix array (DMA) TEG for statistical analysis. It is found that, in the tail part of the distribution, threshold voltage change by RTN (ΔVth) in FD SOI MOSFETs is smaller than that in Bulk MOSFETs. 3D device simulation confirms that ΔVth becomes very large in bulk MOSFETs when a trap happens to be in the valley of channel potential caused by random dopant fluctuation (RDF), while the possibility of large ΔVth is small in FD SOI MOSFETs because the channel potential profile is smooth due to low impurity density.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129663260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757985
KahHou Chan, B. Benbakhti, C. Riddet, J. Watling, A. Asenov
The use of high mobility channel materials such as Germanium can increase the pMOSFET drive current, thus improving the switching speed of CMOS. In this study the impact of the lateral spacer thickness on the performance of a 20 nm gate-length implant-free quantum well (IFQW) Ge pMOSFET is investigated using comprehensive full-band Monte Carlo simulations. The results of these simulations show that the narrowing of the spacer from 5 nm down to 1 nm leads to a possible ∼ 2.5× increase in drive current.
采用锗等高迁移率的沟道材料可以增加pMOSFET的驱动电流，从而提高CMOS的开关速度。本研究利用蒙特卡罗模拟研究了横向间隔层厚度对20 nm栅长无植入量子阱(IFQW) Ge pMOSFET性能的影响。这些模拟结果表明，将间隔层从5nm缩小到1nm可能导致驱动电流增加约2.5倍。
{"title":"Monte Carlo simulation of a 20 nm gate length implant free quantum well Ge pMOSFET with different lateral spacer width","authors":"KahHou Chan, B. Benbakhti, C. Riddet, J. Watling, A. Asenov","doi":"10.1109/ULIS.2011.5757985","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757985","url":null,"abstract":"The use of high mobility channel materials such as Germanium can increase the pMOSFET drive current, thus improving the switching speed of CMOS. In this study the impact of the lateral spacer thickness on the performance of a 20 nm gate-length implant-free quantum well (IFQW) Ge pMOSFET is investigated using comprehensive full-band Monte Carlo simulations. The results of these simulations show that the narrowing of the spacer from 5 nm down to 1 nm leads to a possible ∼ 2.5× increase in drive current.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130056676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758018
J. Dura, S. Martinie, D. Munteanu, F. Triozon, S. Barraud, Y. Niquet, J. Barbe, J. Autran
Gate-All-Around (GAA) nanowire architecture is aimed to represent the ultimate integration for MOSFET up to dimensions of several nanometers. Very thin nanowires (< 5 nm) are expected to be used in these ultimate devices, for which a new physical phenomenon emerges: the modification of the band structure compared to bulk silicon, which changes the conduction properties and affects the device characteristics. These band structure effects (BSE) are then expected to influence the performances of circuits based on ultra-thin nanowire GAA MOSFETs. In this paper, an analytical model for ballistic current in GAA nanowire MOSFET including the band structure variation is developed to assess the BSE impact on nanowire MOSFET operation. Results at the device level are successfully confronted and validated on numerical tight-binding simulations. The model is further implemented in a circuit simulator and is used to evaluate BSE impact on performances of ring oscillator based on GAA nanowire MOSFET.
{"title":"Analytical model of ballistic current for GAA nanowire MOSFET including band structure effects: Application to ring oscillator","authors":"J. Dura, S. Martinie, D. Munteanu, F. Triozon, S. Barraud, Y. Niquet, J. Barbe, J. Autran","doi":"10.1109/ULIS.2011.5758018","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758018","url":null,"abstract":"Gate-All-Around (GAA) nanowire architecture is aimed to represent the ultimate integration for MOSFET up to dimensions of several nanometers. Very thin nanowires (< 5 nm) are expected to be used in these ultimate devices, for which a new physical phenomenon emerges: the modification of the band structure compared to bulk silicon, which changes the conduction properties and affects the device characteristics. These band structure effects (BSE) are then expected to influence the performances of circuits based on ultra-thin nanowire GAA MOSFETs. In this paper, an analytical model for ballistic current in GAA nanowire MOSFET including the band structure variation is developed to assess the BSE impact on nanowire MOSFET operation. Results at the device level are successfully confronted and validated on numerical tight-binding simulations. The model is further implemented in a circuit simulator and is used to evaluate BSE impact on performances of ring oscillator based on GAA nanowire MOSFET.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128880466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757980
L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
{"title":"Atomic scale simulation of a junctionless silicon nanowire transistor","authors":"L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer","doi":"10.1109/ULIS.2011.5757980","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757980","url":null,"abstract":"We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757954
M. Cheralathan, C. Sampedro, J. Roldán, F. Gámiz, G. Iannaccone, E. Sangiorgi, B. Iñíguez
In this paper we extend a Double Gate (DG) MOSFET model to nanometer technology nodes in order to include the hydrodynamic and quantum mechanical effects, and we show that the final model can accurately reproduce simulation results of the advanced transport models. Template devices representative of 22nm and 16nm DG MOSFETs were used to validate the model. The final model includes the main short-channel and nanoscale effects, such as mobility degradation, channel length modulation, drain-induced barrier lowering, overshoot velocity effects and quantum mechanical effects.
{"title":"Analytical drain current model reproducing advanced transport models in nanoscale double-gate (DG) MOSFETs","authors":"M. Cheralathan, C. Sampedro, J. Roldán, F. Gámiz, G. Iannaccone, E. Sangiorgi, B. Iñíguez","doi":"10.1109/ULIS.2011.5757954","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757954","url":null,"abstract":"In this paper we extend a Double Gate (DG) MOSFET model to nanometer technology nodes in order to include the hydrodynamic and quantum mechanical effects, and we show that the final model can accurately reproduce simulation results of the advanced transport models. Template devices representative of 22nm and 16nm DG MOSFETs were used to validate the model. The final model includes the main short-channel and nanoscale effects, such as mobility degradation, channel length modulation, drain-induced barrier lowering, overshoot velocity effects and quantum mechanical effects.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113997822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757990
Po-Hsieh Lin, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang
In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better ION-IOFF current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (VG) and drain current (ID) as well as the overdrive voltage (VOV). In addition, the total gate capacitance (Cgg) is also reported.
{"title":"RF performance of the novel planar-type body-connected FinFET fabricated by isolation-last and self-alignment process","authors":"Po-Hsieh Lin, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang","doi":"10.1109/ULIS.2011.5757990","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757990","url":null,"abstract":"In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better I<inf>ON</inf>-I<inf>OFF</inf> current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (V<inf>G</inf>) and drain current (I<inf>D</inf>) as well as the overdrive voltage (V<inf>OV</inf>). In addition, the total gate capacitance (C<inf>gg</inf>) is also reported.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"485 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123557869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758001
V. Djara, K. Cherkaoui, K. Thomas, E. Pelucchi, D. O'Connell, L. Floyd, P. Hurley
We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (Rs) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process was 715°C for 32 s, leading to a minimum Rs of (195.6 ± 3.4) Ω/d. Metal-oxide-semiconductor capacitors (MOSCAPs) with a 2 nm Al2O3 / 8 nm HfO2 gate oxide were annealed at 675°C, 700°C and 725°C for 30 s. Leakage current lower than 2.1×10−8 A/cm2 were obtained for electric fields of ∼3 MV/cm and low frequency dispersion of capacitance in accumulation (<1.7%) were obtained. Densities of interface states (DIT) were estimated using the conductance method. The output characteristics of a 5-μm gate length MOSFET annealed at 650°C is presented.
{"title":"Annealing investigations for high-k first n-channel In0.53Ga0.47As MOSFET development","authors":"V. Djara, K. Cherkaoui, K. Thomas, E. Pelucchi, D. O'Connell, L. Floyd, P. Hurley","doi":"10.1109/ULIS.2011.5758001","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758001","url":null,"abstract":"We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (R<inf>s</inf>) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process was 715°C for 32 s, leading to a minimum R<inf>s</inf> of (195.6 ± 3.4) Ω/d. Metal-oxide-semiconductor capacitors (MOSCAPs) with a 2 nm Al<inf>2</inf>O<inf>3</inf> / 8 nm HfO<inf>2</inf> gate oxide were annealed at 675°C, 700°C and 725°C for 30 s. Leakage current lower than 2.1×10<sup>−8</sup> A/cm<sup>2</sup> were obtained for electric fields of ∼3 MV/cm and low frequency dispersion of capacitance in accumulation (<1.7%) were obtained. Densities of interface states (D<inf>IT</inf>) were estimated using the conductance method. The output characteristics of a 5-μm gate length MOSFET annealed at 650°C is presented.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757952
A. Nichau, E. D. Ozben, M. Schnee, J. Lopes, A. Besmehn, M. Luysberg, L. Knoll, S. Habicht, V. Mussmann, R. Lupták, S. Lenk, J. Rubio‐Zuazo, G. Castro, D. Buca, Q. Zhao, J. Schubert, S. Mantl
The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO3 in a gatefirst MOSFET process on SOI is shown.
{"title":"Lanthanum Lutetium oxide integration in a gate-first process on SOI MOSFETs","authors":"A. Nichau, E. D. Ozben, M. Schnee, J. Lopes, A. Besmehn, M. Luysberg, L. Knoll, S. Habicht, V. Mussmann, R. Lupták, S. Lenk, J. Rubio‐Zuazo, G. Castro, D. Buca, Q. Zhao, J. Schubert, S. Mantl","doi":"10.1109/ULIS.2011.5757952","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757952","url":null,"abstract":"The chemical reactions at the higher-k LaLuO<inf>3</inf>/Ti<inf>1</inf>N<inf>X</inf>/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO<inf>3</inf> with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO<inf>3</inf> in a gatefirst MOSFET process on SOI is shown.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758011
J. Sturm, Y. Huang, L. Han, T. Liu, B. Hekmatshoar, K. Cherenack, E. Lausecker, S. Wagner
While crystalline silicon FET's are the key enablers for the integrated circuit field, amorphous silicon thin film transistors are the key semiconductor of the large-area electronics field, also known as “macroelectronics.” This talk reviews the basic properties of amorphous silicon, and then outlines research trends, driven in large part by new applications. These trends include increased performance, increased stability for analog and high duty cycle applications, flexible substrates for products with new form factors, printing for cost reduction, and crystalline silicon-amorphous silicon interfaces for high performance solar cells.
{"title":"Amorphous silicon: The other silicon","authors":"J. Sturm, Y. Huang, L. Han, T. Liu, B. Hekmatshoar, K. Cherenack, E. Lausecker, S. Wagner","doi":"10.1109/ULIS.2011.5758011","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758011","url":null,"abstract":"While crystalline silicon FET's are the key enablers for the integrated circuit field, amorphous silicon thin film transistors are the key semiconductor of the large-area electronics field, also known as “macroelectronics.” This talk reviews the basic properties of amorphous silicon, and then outlines research trends, driven in large part by new applications. These trends include increased performance, increased stability for analog and high duty cycle applications, flexible substrates for products with new form factors, printing for cost reduction, and crystalline silicon-amorphous silicon interfaces for high performance solar cells.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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