{"title":"Optimized design method for full-custom microprocessors","authors":"K. Usami, J. Iwamura","doi":"10.1109/CICC.1989.56790","DOIUrl":null,"url":null,"abstract":"An effective design method for VLSI-based microprocessors is proposed. The chip is divided into three components, namely control logic, data paths, and macrocells, at a very early stage. The control logic is automatically designed by logic synthesis and automatic placement and routing. For the data paths and the macrocells, logic and layout are designed manually. By combining the design method with so-called design-pipelining, a 32-bit microprocessor with 460 K transistors was designed in a year without sacrificing the chip size and performance. The method's impact on design effort is also discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
An effective design method for VLSI-based microprocessors is proposed. The chip is divided into three components, namely control logic, data paths, and macrocells, at a very early stage. The control logic is automatically designed by logic synthesis and automatic placement and routing. For the data paths and the macrocells, logic and layout are designed manually. By combining the design method with so-called design-pipelining, a 32-bit microprocessor with 460 K transistors was designed in a year without sacrificing the chip size and performance. The method's impact on design effort is also discussed