A novel test structure to implement a programmable logic array using split-gate flash memory cells

Abstract

We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash® configuration element (SCE) has been demonstrated with a 90nm embedded Flash technology. The resulting SCE eliminates the need for esoteric fabrication process, and sensing, and SRAM circuits and reduces configuration time for programmable arrays (PA) such as FPGAs and CPLDs. Additionally, SCE inherently ports the advantages of SST's split-gate Flash memory technology with compact area, low-voltage read operation, low-power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, along with superior reliability.