Vertical Slit Transistor based Integrated Circuits (VeSTICs)

Abstract

Vertical slit 3D device architecture, proposed by W. Maly, can be shared by a variety of different types of transistors including a new junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs). Proposed new IC design/manufacturing paradigm can deliver high manufacturing efficiency (as has been achieved by memory producers) combined with fast and inexpensive design.