Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724641
Martin Strava
This paper presents a novel online fault tolerance method for network-on-chip (NoC) interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. Another concept of monitoring errors separately on two types of interconnects – inter-switch links and intra-switch input/output port paths – is also employed. The concept introduced allows more efficient routing in comparison to existing error recovery schemes. Experimental validation shows that the proposed NoC error recovery scheme utilising both the concepts delivers better or at least similar performance when compared to existing NoC error recovery schemes.
{"title":"Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures","authors":"Martin Strava","doi":"10.1109/DDECS.2019.8724641","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724641","url":null,"abstract":"This paper presents a novel online fault tolerance method for network-on-chip (NoC) interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. Another concept of monitoring errors separately on two types of interconnects – inter-switch links and intra-switch input/output port paths – is also employed. The concept introduced allows more efficient routing in comparison to existing error recovery schemes. Experimental validation shows that the proposed NoC error recovery scheme utilising both the concepts delivers better or at least similar performance when compared to existing NoC error recovery schemes.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122033846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/DDECS.2014.6868751
Y. Zorian
{"title":"Detection & diagnostics in today's advanced technology nodes","authors":"Y. Zorian","doi":"10.1109/DDECS.2014.6868751","DOIUrl":"https://doi.org/10.1109/DDECS.2014.6868751","url":null,"abstract":"","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133021578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-08DOI: 10.1109/DDECS.2013.6549775
R. Drechsler, Mathias Soeken
Modern systems consisting of hardware and software are becoming more and more complex. The underlying data of next generation systems will consist of billions of entries in terms of components or lines of code. Handling this data efficiently is one of the major challenges for future EDA. In order to provide a meaningful preparation for these complex issues it is inevitable to deal with highly elaborated visualization techniques. It is unimaginable how data sets of this size could be grasped without advanced plotting methods. Although a lot of effort has been put into research for visualization of hardware and software, techniques hardly exist that consider them in combination. Besides that, in most cases visualization techniques concentrate on the illustration of the system's structure and behavior, e.g. to ease debugging. However, far more information can be integrated. As an example, in the context of verification the accentuation of coverage metrics on top of the structural visualization of a system would immediately pinpoint the verification engineer to areas that are poorly validated. Furthermore, when considering the co-design of hardware-software systems, design exploration can be carried out much easier when the designer gets immediate visual feedback. Inspired by recent achievements in visualization methods and the invention of sophisticated machinery, in this invited paper we propose the use of Hardware-Software Co-Visualization (HSCV). The potential of current techniques as well as their limitations will be demonstrated. Furthermore, we are seeking for alternative methods in system visualization that go beyond monitors and printed pages. Techniques from 3D rendering and virtual reality are utilized for this purpose leading to a holistic environment in which complex systems can be grasped within seconds just as huge data sets in the context of plots. State-of-the-art is presented and directions for future work are outlined.
{"title":"Hardware-Software Co-Visualization: Developing systems in the holodeck","authors":"R. Drechsler, Mathias Soeken","doi":"10.1109/DDECS.2013.6549775","DOIUrl":"https://doi.org/10.1109/DDECS.2013.6549775","url":null,"abstract":"Modern systems consisting of hardware and software are becoming more and more complex. The underlying data of next generation systems will consist of billions of entries in terms of components or lines of code. Handling this data efficiently is one of the major challenges for future EDA. In order to provide a meaningful preparation for these complex issues it is inevitable to deal with highly elaborated visualization techniques. It is unimaginable how data sets of this size could be grasped without advanced plotting methods. Although a lot of effort has been put into research for visualization of hardware and software, techniques hardly exist that consider them in combination. Besides that, in most cases visualization techniques concentrate on the illustration of the system's structure and behavior, e.g. to ease debugging. However, far more information can be integrated. As an example, in the context of verification the accentuation of coverage metrics on top of the structural visualization of a system would immediately pinpoint the verification engineer to areas that are poorly validated. Furthermore, when considering the co-design of hardware-software systems, design exploration can be carried out much easier when the designer gets immediate visual feedback. Inspired by recent achievements in visualization methods and the invention of sophisticated machinery, in this invited paper we propose the use of Hardware-Software Co-Visualization (HSCV). The potential of current techniques as well as their limitations will be demonstrated. Furthermore, we are seeking for alternative methods in system visualization that go beyond monitors and printed pages. Techniques from 3D rendering and virtual reality are utilized for this purpose leading to a holistic environment in which complex systems can be grasped within seconds just as huge data sets in the context of plots. State-of-the-art is presented and directions for future work are outlined.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121631868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-18DOI: 10.1109/DDECS.2012.6219008
S. Hamdioui
The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test.
{"title":"TSV based 3D stacked ICs: Opportunities and challenges","authors":"S. Hamdioui","doi":"10.1109/DDECS.2012.6219008","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219008","url":null,"abstract":"The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"66 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127257791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-18DOI: 10.1109/DDECS.2012.6219007
M. Reorda
On-line test of embedded systems is becoming increasingly important mainly due to the growing usage of electronic systems in safety-critical applications and to the higher chances of failures in new devices. Standards and regulations are also pushing the adoption of effective on-line test solutions both at the device and at the system level. While Design for On-Line Testability is definitely an effective solution, there are situations in which alternative or complementary ways have to be explored, and functional testing stands as the only viable solution. The presentation will overview the main open issues in this area (e.g., in terms of achievable defect coverage, test time, and costs), emphasizing the limitations of the functional approach, but also reporting about recent advancements that could allow its easier and wider adoption in practice.
{"title":"On-line test of embedded systems: Which role for functional test?","authors":"M. Reorda","doi":"10.1109/DDECS.2012.6219007","DOIUrl":"https://doi.org/10.1109/DDECS.2012.6219007","url":null,"abstract":"On-line test of embedded systems is becoming increasingly important mainly due to the growing usage of electronic systems in safety-critical applications and to the higher chances of failures in new devices. Standards and regulations are also pushing the adoption of effective on-line test solutions both at the device and at the system level. While Design for On-Line Testability is definitely an effective solution, there are situations in which alternative or complementary ways have to be explored, and functional testing stands as the only viable solution. The presentation will overview the main open issues in this area (e.g., in terms of achievable defect coverage, test time, and costs), emphasizing the limitations of the functional approach, but also reporting about recent advancements that could allow its easier and wider adoption in practice.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783033
J. Alt
During history of semiconductor development Computer-Aided Design developed into Electronic Design Automation. Point tools provided by CAD/EDA industry were selected by industrial design flows and integrated to make use of best-in class tools available for product development. This was a useful approach to target the classical focus segments for semiconductor design: area, verification and technology enabling. During the last years additional design parameters like power optimization have been introduced successfully into industrial design flows. There is still a need to improve tools addressing these technical design constraints within the foreseeable future.
{"title":"Future of EDA: Usual suspect or silent hero for successful semiconductor business?","authors":"J. Alt","doi":"10.1109/DDECS.2011.5783033","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783033","url":null,"abstract":"During history of semiconductor development Computer-Aided Design developed into Electronic Design Automation. Point tools provided by CAD/EDA industry were selected by industrial design flows and integrated to make use of best-in class tools available for product development. This was a useful approach to target the classical focus segments for semiconductor design: area, verification and technology enabling. During the last years additional design parameters like power optimization have been introduced successfully into industrial design flows. There is still a need to improve tools addressing these technical design constraints within the foreseeable future.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012085
A. Chatterjee
CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst case operating conditions (e.g. environmental noise). This forces designers to excessively guard band their circuits while using “aggressive” back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are cognitive of their environmental operating conditions and manufacturing process conditions and use this cognition to perform self-adaptation that conserves power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation. This talk summarizes recent results obtained in the design of such cognitive computing and communication systems and points to directions for future work in this area.
{"title":"Cognitive self-adaptive computing and communication systems: Test, control and adaptation","authors":"A. Chatterjee","doi":"10.1109/DDECS.2009.5012085","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012085","url":null,"abstract":"CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst case operating conditions (e.g. environmental noise). This forces designers to excessively guard band their circuits while using “aggressive” back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are cognitive of their environmental operating conditions and manufacturing process conditions and use this cognition to perform self-adaptation that conserves power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation. This talk summarizes recent results obtained in the design of such cognitive computing and communication systems and points to directions for future work in this area.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125451095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012086
A. Chichkov
If test is mentioned normally there are several remarks that have been repeated for the last 20 years. ICs are too fast, patterns are too big, testing is too slow, the test development too costly. Although, the advance of the technology has improved test in general, these statements seems to prevail and sound still valid. One reason is that on every improvement of test strategies there is also improvement of technology and design strategy that keeps the gap open. On the other hand ATE equipment inevitably is build with one generation older technology that keeps the challenge of speed noise and complexity alive. In this presentation the following few challenges for test will be further discussed. How is evolving the gap between test methods tools and equipment on one side and technology, design methodology and design tools on the other? How is evolving the cost of production test equipment and as consequence the cost of test? Is there change in the cost of test development? What about high quality and reliability application testing? And last but not least what about research in the test domain during economic crisis.
{"title":"Challenges for test and design for test","authors":"A. Chichkov","doi":"10.1109/DDECS.2009.5012086","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012086","url":null,"abstract":"If test is mentioned normally there are several remarks that have been repeated for the last 20 years. ICs are too fast, patterns are too big, testing is too slow, the test development too costly. Although, the advance of the technology has improved test in general, these statements seems to prevail and sound still valid. One reason is that on every improvement of test strategies there is also improvement of technology and design strategy that keeps the gap open. On the other hand ATE equipment inevitably is build with one generation older technology that keeps the challenge of speed noise and complexity alive. In this presentation the following few challenges for test will be further discussed. How is evolving the gap between test methods tools and equipment on one side and technology, design methodology and design tools on the other? How is evolving the cost of production test equipment and as consequence the cost of test? Is there change in the cost of test development? What about high quality and reliability application testing? And last but not least what about research in the test domain during economic crisis.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128502456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012084
G. Gielen
With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Design tools for the efficient analysis and identification of reliability problems in analog circuits is described. Also, run-time circuit adaptation techniques are presented that allow a circuit to recover from degradation failures.
{"title":"Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS","authors":"G. Gielen","doi":"10.1109/DDECS.2009.5012084","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012084","url":null,"abstract":"With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Design tools for the efficient analysis and identification of reliability problems in analog circuits is described. Also, run-time circuit adaptation techniques are presented that allow a circuit to recover from degradation failures.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128131740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-04-16DOI: 10.1109/DDECS.2008.4538742
K. Flautner
Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with continual improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features.
{"title":"The Wall Ahead is Made of Rubber","authors":"K. Flautner","doi":"10.1109/DDECS.2008.4538742","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538742","url":null,"abstract":"Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with continual improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features.","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115655099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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