Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology

Abstract

Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS.<>