S. Venkatesan, Chitra K. Subramanian, G. Neudeck, J. Denton
Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications of SOI devices have extended to the field of power devices and mixed-mode analog-digital circuits. In this field of application in particular, selective epitaxial growth techniques such as epitaxial lateral overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG) provide attractive alternatives to SIMOX. ELO and CLSEG provide the means of selectively growing SOI islands in regions where high performance digital MOS circuitry are desired. Due to the low temperatures involved in selective epitaxy, mixed mode integration becomes a lot easier. This paper presents results from fully-depleted SOI devices fabricated by ELO and provides for the first time a study of interface state densities across the various interfaces in the device. In addition, thin-film fully-depleted SOI devices have been fabricated for the first time in SOI device islands fabricated by CLSEG, and the devices have been used to characterize the material.<>
{"title":"Thin-film silicon-on-insulator (SOI) device applications of selective epitaxial growth","authors":"S. Venkatesan, Chitra K. Subramanian, G. Neudeck, J. Denton","doi":"10.1109/SOI.1993.344584","DOIUrl":"https://doi.org/10.1109/SOI.1993.344584","url":null,"abstract":"Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications of SOI devices have extended to the field of power devices and mixed-mode analog-digital circuits. In this field of application in particular, selective epitaxial growth techniques such as epitaxial lateral overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG) provide attractive alternatives to SIMOX. ELO and CLSEG provide the means of selectively growing SOI islands in regions where high performance digital MOS circuitry are desired. Due to the low temperatures involved in selective epitaxy, mixed mode integration becomes a lot easier. This paper presents results from fully-depleted SOI devices fabricated by ELO and provides for the first time a study of interface state densities across the various interfaces in the device. In addition, thin-film fully-depleted SOI devices have been fabricated for the first time in SOI device islands fabricated by CLSEG, and the devices have been used to characterize the material.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115149659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Anc, B.F. Cordts, L. Allen, W. Krull, M. Guerra
In this paper we will discuss aspects of directional or crystallographic effects in implantation of oxygen, with emphasis on the possibility of effects of pinhole formation due to the channeling phenomenon, and application of the intentionally channeled implant to obtain better properties of thin film layers.<>
{"title":"Crystallographic effects in implantation of oxygen for SIMOX","authors":"M. Anc, B.F. Cordts, L. Allen, W. Krull, M. Guerra","doi":"10.1109/SOI.1993.344599","DOIUrl":"https://doi.org/10.1109/SOI.1993.344599","url":null,"abstract":"In this paper we will discuss aspects of directional or crystallographic effects in implantation of oxygen, with emphasis on the possibility of effects of pinhole formation due to the channeling phenomenon, and application of the intentionally channeled implant to obtain better properties of thin film layers.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121834396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital circuitry that would perform reliably in adverse high temperature environments is needed in applications that include under-the-hood and anti-lock braking automotive functions as well as distributed jet engine control applications. Careful circuit design practices coupled with a good understanding of how these devices perform at, elevated temperatures would allow the development of these circuit functions for reliable, long term operation in these environments. This paper describes the high temperature (to 400/spl deg/C) testing and characterization of a number of parametric test structures fabricated using United Technologies Microelectronics Center's Digital CMOS SOI (DCS) process. This technology was designed for high performance, low power, high temperature, and radiation hardened applications at conventional and reduced power supply voltage levels.<>
数字电路需要在恶劣的高温环境中可靠地工作，包括引擎盖下和防抱死制动汽车功能以及分布式喷气发动机控制应用。仔细的电路设计实践加上对这些设备在高温下的性能的良好理解，将允许这些电路功能在这些环境中可靠、长期运行的发展。本文介绍了使用联合技术微电子中心的数字CMOS SOI (DCS)工艺制造的一些参数化测试结构的高温(至400/spl℃)测试和表征。该技术专为高性能、低功耗、高温和抗辐射应用而设计，适用于传统和降低电源电压水平。
{"title":"High temperature testing of SOI devices to 400/spl deg/C","authors":"R. Grzybowski, S.M. Tyson","doi":"10.1109/SOI.1993.344547","DOIUrl":"https://doi.org/10.1109/SOI.1993.344547","url":null,"abstract":"Digital circuitry that would perform reliably in adverse high temperature environments is needed in applications that include under-the-hood and anti-lock braking automotive functions as well as distributed jet engine control applications. Careful circuit design practices coupled with a good understanding of how these devices perform at, elevated temperatures would allow the development of these circuit functions for reliable, long term operation in these environments. This paper describes the high temperature (to 400/spl deg/C) testing and characterization of a number of parametric test structures fabricated using United Technologies Microelectronics Center's Digital CMOS SOI (DCS) process. This technology was designed for high performance, low power, high temperature, and radiation hardened applications at conventional and reduced power supply voltage levels.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124859418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Soderbarg, B. Edholm, J. Olsson, S. Tiensuu, E. Johansson
In this abstract a concept is presented aimed to increase the heat distribution and to reduce the thermal resistance in SOI-devices. This is realized using a combination of fusion bonding and thinning against stopping layers with deposition of poly-crystalline diamond as the buried isolator. Thus, by replacing oxide with diamond, a Silicon-on-Diamond (SOD) structure is formed.<>
{"title":"Silicon on diamond heat sinks by bonding and etch back","authors":"A. Soderbarg, B. Edholm, J. Olsson, S. Tiensuu, E. Johansson","doi":"10.1109/SOI.1993.344593","DOIUrl":"https://doi.org/10.1109/SOI.1993.344593","url":null,"abstract":"In this abstract a concept is presented aimed to increase the heat distribution and to reduce the thermal resistance in SOI-devices. This is realized using a combination of fusion bonding and thinning against stopping layers with deposition of poly-crystalline diamond as the buried isolator. Thus, by replacing oxide with diamond, a Silicon-on-Diamond (SOD) structure is formed.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SiC is an attractive material for applications requiring high operation conditions of temperature, speed, power and radiation. For these purposes, SiC has several materials properties superior to Si: wider band-gap, higher breakdown field, higher saturated electron drift velocity and higher thermal conductivity. However, the cost of bulk SiC crystals is extremely high and the size of the wafer is presently still limited to 2 inch in diameter. The purpose of this work is to study the feasibility of using wafer bonding approach to transfer SiC layers grown by CVD on silicon to insulating substrates, such as oxidized silicon or sapphire. Since the quality of CVD SiC layers on silicon has been improved significantly, the transfer technology could possibly drastically reduce the cost and provide a great flexibility to explore the potential offered by SiC in many application areas: high frequency and/or rad-hard electronic devices, visible optical wave guides and planar displays.<>
{"title":"A feasibility study of SiC on oxide by wafer bonding and layer transferring","authors":"Q. Tong, U. Gosele, C. Yuan, A. Steckl","doi":"10.1109/SOI.1993.344592","DOIUrl":"https://doi.org/10.1109/SOI.1993.344592","url":null,"abstract":"SiC is an attractive material for applications requiring high operation conditions of temperature, speed, power and radiation. For these purposes, SiC has several materials properties superior to Si: wider band-gap, higher breakdown field, higher saturated electron drift velocity and higher thermal conductivity. However, the cost of bulk SiC crystals is extremely high and the size of the wafer is presently still limited to 2 inch in diameter. The purpose of this work is to study the feasibility of using wafer bonding approach to transfer SiC layers grown by CVD on silicon to insulating substrates, such as oxidized silicon or sapphire. Since the quality of CVD SiC layers on silicon has been improved significantly, the transfer technology could possibly drastically reduce the cost and provide a great flexibility to explore the potential offered by SiC in many application areas: high frequency and/or rad-hard electronic devices, visible optical wave guides and planar displays.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"43 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114102279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, self-heating effects are studied as a function of temperature. The electrical properties of fully depleted thin Si film N- and P-channel SIMOX MOSFETs are investigated between room and liquid helium temperatures. The P-and N-channel devices used in this study have been fabricated at LETI (Grenoble) with a conventionally-doped and a degenerately-doped LDD structures, respectively. The devices have an 11.5 nm gate oxide and a 380 nm buried oxide thicknesses. The article shows the drain current-drain voltage characteristics at 300 K for an N-channel SIMOX MOSFET fabricated with a degenerately doped LDD structure. The characteristics present a low negative differential resistance phenomenon for gate voltage up to 5 V. However, at 77 K, a strong negative differential resistance is observed for high gate voltages. The self heating effects are therefore significantly increased by reducing the temperature. This dependence is supposed to be due to the mobility variations and, also, the change with temperature of the threshold voltage.<>
在这项工作中，研究了自热效应与温度的函数关系。研究了完全耗尽型硅薄膜 N 沟道和 P 沟道 SIMOX MOSFET 在室温和液氦温度之间的电气特性。本研究中使用的 P 沟道和 N 沟道器件是在 LETI（格勒诺布尔）分别采用传统掺杂和变性掺杂 LDD 结构制造的。这些器件的栅极氧化层厚度为 11.5 nm，埋层氧化层厚度为 380 nm。文章展示了采用变性掺杂 LDD 结构制造的 N 沟道 SIMOX MOSFET 在 300 K 时的漏极电流-漏极电压特性。在栅极电压高达 5 V 时，该特性呈现出较低的负差分电阻现象。然而，在 77 K 时，高栅极电压会产生较强的负差分电阻。因此，降低温度会显著增加自加热效应。这种依赖性应归因于迁移率的变化，以及阈值电压随温度的变化。
{"title":"Self-heating effects in SOI MOSFET's operated at low temperature","authors":"J. Jomaah, F. Balestra, G. Ghibaudo","doi":"10.1109/SOI.1993.344581","DOIUrl":"https://doi.org/10.1109/SOI.1993.344581","url":null,"abstract":"In this work, self-heating effects are studied as a function of temperature. The electrical properties of fully depleted thin Si film N- and P-channel SIMOX MOSFETs are investigated between room and liquid helium temperatures. The P-and N-channel devices used in this study have been fabricated at LETI (Grenoble) with a conventionally-doped and a degenerately-doped LDD structures, respectively. The devices have an 11.5 nm gate oxide and a 380 nm buried oxide thicknesses. The article shows the drain current-drain voltage characteristics at 300 K for an N-channel SIMOX MOSFET fabricated with a degenerately doped LDD structure. The characteristics present a low negative differential resistance phenomenon for gate voltage up to 5 V. However, at 77 K, a strong negative differential resistance is observed for high gate voltages. The self heating effects are therefore significantly increased by reducing the temperature. This dependence is supposed to be due to the mobility variations and, also, the change with temperature of the threshold voltage.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"724 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is a goal of electronic materials fabrication efforts to produce SIMOX with a low dislocation density in the superficial Si layer (the device layer) as well as a buried oxide (BOX) layer consisting of high quality SiO/sub 2/. In this paper, we study the effects of varying the implantation angle in a search for the optimal implantation conditions from the standpoint of both the BOX and the device layer. Using transmission electron microscopy (TEM) and spectroscopic ellipsometry (SE), we show that there is a significant difference between channeled and unchanneled implantation in SIMOX.<>
{"title":"Characterization of SIMOX material with channeled and unchanneled oxygen implantation","authors":"M. Twigg, L. Allen, B.J. Mrstik, L.T. Ardis","doi":"10.1109/SOI.1993.344597","DOIUrl":"https://doi.org/10.1109/SOI.1993.344597","url":null,"abstract":"It is a goal of electronic materials fabrication efforts to produce SIMOX with a low dislocation density in the superficial Si layer (the device layer) as well as a buried oxide (BOX) layer consisting of high quality SiO/sub 2/. In this paper, we study the effects of varying the implantation angle in a search for the optimal implantation conditions from the standpoint of both the BOX and the device layer. Using transmission electron microscopy (TEM) and spectroscopic ellipsometry (SE), we show that there is a significant difference between channeled and unchanneled implantation in SIMOX.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114301838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present results of a comprehensive study of the subthreshold characteristics of deep-submicron fully depleted SOI MOSFETs, and suggest optimal CMOS scaling rules based on PISCES simulations and two-dimensional analytic modeling for circuit simulation. Measurements reveal that the subthreshold swing S, which is nearly ideal at 60 mV for long-channel fully depleted devices, tends to increase drastically as L is scaled to deep-submicron values. Our previous study showed that the front-surface current contributes to the increased S via gate bias-dependent source/drain charge sharing, which reduces the effective threshold voltage. A more recent study shows that current throughout the SOI film body, including the back surface, tends to overwhelm the front-surface current in the subthreshold region, rendering the drain current less dependent on the front-gate bias and hence increasing S even more.<>
{"title":"Subthreshold MOSFET conduction model and optimal scaling for deep-submicron fully depleted SOI CMOS","authors":"P. Yeh, J. Fossum","doi":"10.1109/SOI.1993.344560","DOIUrl":"https://doi.org/10.1109/SOI.1993.344560","url":null,"abstract":"In this paper we present results of a comprehensive study of the subthreshold characteristics of deep-submicron fully depleted SOI MOSFETs, and suggest optimal CMOS scaling rules based on PISCES simulations and two-dimensional analytic modeling for circuit simulation. Measurements reveal that the subthreshold swing S, which is nearly ideal at 60 mV for long-channel fully depleted devices, tends to increase drastically as L is scaled to deep-submicron values. Our previous study showed that the front-surface current contributes to the increased S via gate bias-dependent source/drain charge sharing, which reduces the effective threshold voltage. A more recent study shows that current throughout the SOI film body, including the back surface, tends to overwhelm the front-surface current in the subthreshold region, rendering the drain current less dependent on the front-gate bias and hence increasing S even more.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high-quality SIMOX wafer with an extremely low dislocation density, less than 300 cm/sup -2/ has been formed at low doses of between 3.0 x 10/sup 17/ and 5.0 x 10/sup 17/ cm/sup -2/. This wafer should open the way to practical fabrication of SIMOX ULSIs. The buried oxide layer of this wafer, however, has a relatively low breakdown electric field strength of around 4 MV/cm. The authors clarify the cause of this low breakdown field and propose a method for improving it.<>
{"title":"Improvement of the breakdown field of SIMOX buried oxide layers","authors":"S. Nakashima, M. Harada, T. Tsuchiya","doi":"10.1109/SOI.1993.344611","DOIUrl":"https://doi.org/10.1109/SOI.1993.344611","url":null,"abstract":"A high-quality SIMOX wafer with an extremely low dislocation density, less than 300 cm/sup -2/ has been formed at low doses of between 3.0 x 10/sup 17/ and 5.0 x 10/sup 17/ cm/sup -2/. This wafer should open the way to practical fabrication of SIMOX ULSIs. The buried oxide layer of this wafer, however, has a relatively low breakdown electric field strength of around 4 MV/cm. The authors clarify the cause of this low breakdown field and propose a method for improving it.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Faynot, L. T. Su, S. Cristoloveanu, C. Raynaud, J. E. Chung, A. Auberton-Herve, D. Antoniadis
It is demonstrated that ultra-thin film (UTF) inversion-mode (IM) and accumulation-mode (AM) SIMOX MOSFETs behave similarly in terms of hot-carrier degradation. The primary degradation occurs at the interface which is activated but the effects of interface coupling can confuse lifetime predictions. Defects (such as in the buried oxide) must be clearly accounted for and decoupled in order to properly evaluate device lifetime. There was no evidence of significant enhanced degradation in ultra-thin films.<>
{"title":"Comparison of hot-carrier degradation effects in inversion-mode and accumulation-mode fully depleted SOI MOSFETs","authors":"O. Faynot, L. T. Su, S. Cristoloveanu, C. Raynaud, J. E. Chung, A. Auberton-Herve, D. Antoniadis","doi":"10.1109/SOI.1993.344551","DOIUrl":"https://doi.org/10.1109/SOI.1993.344551","url":null,"abstract":"It is demonstrated that ultra-thin film (UTF) inversion-mode (IM) and accumulation-mode (AM) SIMOX MOSFETs behave similarly in terms of hot-carrier degradation. The primary degradation occurs at the interface which is activated but the effects of interface coupling can confuse lifetime predictions. Defects (such as in the buried oxide) must be clearly accounted for and decoupled in order to properly evaluate device lifetime. There was no evidence of significant enhanced degradation in ultra-thin films.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122286164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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