A high-speed low-power pulse-swallow divider with robustness consideration

Abstract

A high-speed low-power programmable pulse-swallow divider is designed and fabricated in SMIC 0.18-¿m CMOS process. Two critical paths that limit the operating frequency are analyzed. The proposed prescaler based on a shift-register-ring is insensitive to the Modulus Control (MC) during its first few input cycles, and thus wrong divide ratio caused by the MC¿s delay can be avoided. The proposed pulse generator works as a sample/hold block to widen the time slot of the reading process, and thus failure in reading external control words into the swallow counter can also be avoided. A 3.5-GHz integer phase-locked loop (PLL) that uses the divider employing the proposed prescaler and pulse generator provides 21 channels with a 1.2-ppm precision in measurements. The power dissipation is 0.475-mW from a 1.2-V supply under 1.6-GHz operating frequency.