Enhancing FPGA security through Trojan resilient IP creation

Abstract

In recent years FPGAs have become vulnerable to hardware Trojan attacks due to their increased use in different applications like defense, automotive, image processing, etc. Among several types of hardware Trojan attacks in FPGAs, one of them is implanting hardware Trojans using the bitstream modification. These types of hardware Trojans exploit the empty resources in FPGA by modifying the original design by bitstream modification. In this paper, Trojan Resilient IP is created by adding original design with the dummy logic design in order to provide security and trust for FPGA-based designs. Covering the unused resources with dummy logic design incurs power and delay overhead for FPGA design when the dummy logic circuit is in operation. This paper also addresses the power and delay overhead for Trojan Resilient IP Creation using different ISACS'89 benchmark circuits.