Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268801
Qianqian Wang, R. Geiger
Hardware Trojans that can be easily embedded in synchronous clock generation circuits typical of what are used in large digital systems are discussed. These Trojans are both visible and transparent. Since they are visible, they will penetrate split-lot manufacturing security methods and their transparency will render existing detection methods ineffective.
{"title":"Visible but transparent hardware Trojans in clock generation circuits","authors":"Qianqian Wang, R. Geiger","doi":"10.1109/NAECON.2017.8268801","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268801","url":null,"abstract":"Hardware Trojans that can be easily embedded in synchronous clock generation circuits typical of what are used in large digital systems are discussed. These Trojans are both visible and transparent. Since they are visible, they will penetrate split-lot manufacturing security methods and their transparency will render existing detection methods ineffective.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122836975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268715
Jianzhe Liu, Wei Zhang, G. Rizzoni
In this paper, we develop a decentralized controller with virtual inductance to improve the robustness of a DC microgrid with constant power loads (CPLs). It is well known that the key to the problem is increasing the damping in the system. The CPLs, on the other hand, exhibit a negative impedance effect that deteriorates the damping. To counteract the CPLs, various methods including centralized and droop control have been developed. However, existing work have strict requirements on information acquisition and impose significant influences on microgrid's operating points. Instead, this paper develops a decentralized controller with virtual inductance that can virtually increases the damping in a DC microgrid and effectively accomplish the robustness enhancement objective without shifting the operating points. A simulation example is shown to demonstrate the efficacy of the proposed method.
{"title":"Virtual inductance for DC microgrids with constant power loads","authors":"Jianzhe Liu, Wei Zhang, G. Rizzoni","doi":"10.1109/NAECON.2017.8268715","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268715","url":null,"abstract":"In this paper, we develop a decentralized controller with virtual inductance to improve the robustness of a DC microgrid with constant power loads (CPLs). It is well known that the key to the problem is increasing the damping in the system. The CPLs, on the other hand, exhibit a negative impedance effect that deteriorates the damping. To counteract the CPLs, various methods including centralized and droop control have been developed. However, existing work have strict requirements on information acquisition and impose significant influences on microgrid's operating points. Instead, this paper develops a decentralized controller with virtual inductance that can virtually increases the damping in a DC microgrid and effectively accomplish the robustness enhancement objective without shifting the operating points. A simulation example is shown to demonstrate the efficacy of the proposed method.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127947663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268744
Yichao Li, Xiaoping Shen, R. Ewing, Jia Li
Terahertz spectroscopy and imaging are a rapidly developed technique with important applications in many areas, such as medical imaging, security, chemistry, biochemistry, astronomy, communications, and manufacturing, to name a few. However, terahertz spectroscopy and imaging produce excessively high dimensional data which is prohibitive for common methods developed in the area of image processing. In this paper, we report our recent study on a novel classifier based on feature extraction using approximate entropy (ApEn). The classifier is initiated by analyzing the complexity of the terahertz spectrum, which is then combined with a deep neural network for material classification. Experimental results show that approximate entropy based features have high sensitive for detecting metal matrix composites, the accuracy of identification is up to 96.3%. Related algorithms for ApEn feature extraction and material classification are illustrated. An optimal parameter-embedding dimension, subject to classification accuracy for ApEn is studied.
{"title":"Terahertz spectroscopic material identification using approximate entropy and deep neural network","authors":"Yichao Li, Xiaoping Shen, R. Ewing, Jia Li","doi":"10.1109/NAECON.2017.8268744","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268744","url":null,"abstract":"Terahertz spectroscopy and imaging are a rapidly developed technique with important applications in many areas, such as medical imaging, security, chemistry, biochemistry, astronomy, communications, and manufacturing, to name a few. However, terahertz spectroscopy and imaging produce excessively high dimensional data which is prohibitive for common methods developed in the area of image processing. In this paper, we report our recent study on a novel classifier based on feature extraction using approximate entropy (ApEn). The classifier is initiated by analyzing the complexity of the terahertz spectrum, which is then combined with a deep neural network for material classification. Experimental results show that approximate entropy based features have high sensitive for detecting metal matrix composites, the accuracy of identification is up to 96.3%. Related algorithms for ApEn feature extraction and material classification are illustrated. An optimal parameter-embedding dimension, subject to classification accuracy for ApEn is studied.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134638401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268747
T. Kebede, Ouboti Djaneye-Boundjou, B. Narayanan, A. Ralescu, David Kapp
Distinguishing and classifying different types of malware is important to better understanding how they can infect computers and devices, the threat level they pose and how to protect against them. In this paper, a system for classifying malware programs is presented. The paper describes the architecture of the system and assesses its performance on a publicly available database (provided by Microsoft for the Microsoft Malware Classification Challenge BIG2015) to serve as a benchmark for future research efforts. First, the malicious programs are preprocessed such that they are visualized as gray scale images. We then make use of an architecture comprised of multiple layers (multiple levels of encoding) to carry out the classification process of those images/programs. We compare the performance of this approach against traditional machine learning and pattern recognition algorithms. Our experimental results show that the deep learning architecture yields a boost in performance over those conventional/standard algorithms. A hold-out validation analysis using the superior architecture shows an accuracy in the order of 99.15%.
{"title":"Classification of Malware programs using autoencoders based deep learning architecture and its application to the microsoft malware Classification challenge (BIG 2015) dataset","authors":"T. Kebede, Ouboti Djaneye-Boundjou, B. Narayanan, A. Ralescu, David Kapp","doi":"10.1109/NAECON.2017.8268747","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268747","url":null,"abstract":"Distinguishing and classifying different types of malware is important to better understanding how they can infect computers and devices, the threat level they pose and how to protect against them. In this paper, a system for classifying malware programs is presented. The paper describes the architecture of the system and assesses its performance on a publicly available database (provided by Microsoft for the Microsoft Malware Classification Challenge BIG2015) to serve as a benchmark for future research efforts. First, the malicious programs are preprocessed such that they are visualized as gray scale images. We then make use of an architecture comprised of multiple layers (multiple levels of encoding) to carry out the classification process of those images/programs. We compare the performance of this approach against traditional machine learning and pattern recognition algorithms. Our experimental results show that the deep learning architecture yields a boost in performance over those conventional/standard algorithms. A hold-out validation analysis using the superior architecture shows an accuracy in the order of 99.15%.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133901053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268742
C. Yakopcic, T. Taha
This paper describes a memristor-based neuromorphic system that can be used for ex-situ training of various multi-layer neural network algorithms. This system is based on an analog neuron circuit that is capable of performing an accurate dot product calculation. The presented ex-situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. Using this weight-to-crossbar mapping approach along with the dot product calculation circuit, complex neural algorithms can be easily implemented using this system. To show the effectiveness and versatility of this circuit, a Multilayer Perceptron (MLP) is trained to perform Sobel edge detection. Following these simulations, an analysis was presented that shows how both memristor accuracy and neuron circuit gain relates to output error. Additionally, this paper discusses how circuit noise and neural network layout contribute to testing accuracy.
{"title":"Memristor crossbar based implementation of a multilayer perceptron","authors":"C. Yakopcic, T. Taha","doi":"10.1109/NAECON.2017.8268742","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268742","url":null,"abstract":"This paper describes a memristor-based neuromorphic system that can be used for ex-situ training of various multi-layer neural network algorithms. This system is based on an analog neuron circuit that is capable of performing an accurate dot product calculation. The presented ex-situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. Using this weight-to-crossbar mapping approach along with the dot product calculation circuit, complex neural algorithms can be easily implemented using this system. To show the effectiveness and versatility of this circuit, a Multilayer Perceptron (MLP) is trained to perform Sobel edge detection. Following these simulations, an analysis was presented that shows how both memristor accuracy and neuron circuit gain relates to output error. Additionally, this paper discusses how circuit noise and neural network layout contribute to testing accuracy.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268754
Balaadithya Uppalapati, M. Ahamed, V. Chodavarapu
We present the design and analysis of a mode-matched disk resonator gyroscope that is characterized by a high quality factor exceeding 1 million. The mode match resonator is designed using geometric compensation technique for reducing frequency split between two degenerate modes. The gyroscope sensor is designed using MEMS Integrated Design for Inertial Sensors (MIDIS) process offered by Teledyne DALSA Semiconductor Incorporated (TDSI). The MIDIS process offers ultra clean wafer-level vacuum encapsulation at 10m Torr. Our disk resonator gyroscope has a circular shape with 600 μm diameter and is made with 40 μm thick single crystal silicon material.
{"title":"Design and analysis of wafer-level vacuum-encapsulated disk resonator gyroscope using a commercial MEMS process","authors":"Balaadithya Uppalapati, M. Ahamed, V. Chodavarapu","doi":"10.1109/NAECON.2017.8268754","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268754","url":null,"abstract":"We present the design and analysis of a mode-matched disk resonator gyroscope that is characterized by a high quality factor exceeding 1 million. The mode match resonator is designed using geometric compensation technique for reducing frequency split between two degenerate modes. The gyroscope sensor is designed using MEMS Integrated Design for Inertial Sensors (MIDIS) process offered by Teledyne DALSA Semiconductor Incorporated (TDSI). The MIDIS process offers ultra clean wafer-level vacuum encapsulation at 10m Torr. Our disk resonator gyroscope has a circular shape with 600 μm diameter and is made with 40 μm thick single crystal silicon material.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268780
H. Xue, Shuo Li, S. Ren
Outsourcing of chip product chain makes hardware vulnerable to being attacked. For example, an attacker who has access to hardware fabrication process can alter the genuine hardware with the insertion of concealed hardware elements (Hardware Trojan). Therefore, microelectronic circuit Hardware Trojan detection becomes a key step of chip production. A power analysis-based power-analysis microelectronic circuit Hardware Trojan detection methodology is proposed in this paper. The detection method is implemented in 90nm CMOS process. Based on simulation results, our proposed technique can detect Hardware Trojans with areas that are 0.013% of the host-circuitry.
{"title":"Power analysis-based Hardware Trojan detection","authors":"H. Xue, Shuo Li, S. Ren","doi":"10.1109/NAECON.2017.8268780","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268780","url":null,"abstract":"Outsourcing of chip product chain makes hardware vulnerable to being attacked. For example, an attacker who has access to hardware fabrication process can alter the genuine hardware with the insertion of concealed hardware elements (Hardware Trojan). Therefore, microelectronic circuit Hardware Trojan detection becomes a key step of chip production. A power analysis-based power-analysis microelectronic circuit Hardware Trojan detection methodology is proposed in this paper. The detection method is implemented in 90nm CMOS process. Based on simulation results, our proposed technique can detect Hardware Trojans with areas that are 0.013% of the host-circuitry.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268785
Liangyu Li, Weisong Wang, E. Shin, T. Quach, G. Subramanyam
Tunable coplanar waveguide interdigital capacitors (IDC) designed with vanadium dioxide (VO2) thin film are presented in this paper. Two different configurations, series IDC and shunt IDC, are proposed. Tunable capacitance can be implemented by the thermally controllable VO2 thin film. The tunability of IDC structures are 95.6% and 85.4% corresponding to the series IDC and shunt IDC, respectively.
{"title":"Design of tunable shunt and series interdigital capacitors based on vanadium dioxide thin film","authors":"Liangyu Li, Weisong Wang, E. Shin, T. Quach, G. Subramanyam","doi":"10.1109/NAECON.2017.8268785","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268785","url":null,"abstract":"Tunable coplanar waveguide interdigital capacitors (IDC) designed with vanadium dioxide (VO2) thin film are presented in this paper. Two different configurations, series IDC and shunt IDC, are proposed. Tunable capacitance can be implemented by the thermally controllable VO2 thin film. The tunability of IDC structures are 95.6% and 85.4% corresponding to the series IDC and shunt IDC, respectively.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268749
Nitin Pundir, Noor Ahmad Hazari, Fathi H. Amsaad, M. Niamat
In this paper, machine learning attacks are performed on a novel hybrid delay based Arbiter Ring Oscillator PUF (AROPUF). The AROPUF exhibits improved results when compared to traditional Arbiter Physical Unclonable Function (APUF). The challenge-response pairs (CRPs) from both PUFs are fed to the multilayered perceptron model (MLP) with one hidden layer. The results show that the CRPs generated from the proposed AROPUF has more training and prediction errors when compared to the APUF, thus making it more difficult for the adversary to predict the CRPs.
{"title":"A novel hybrid delay based physical unclonable function immune to machine learning attacks","authors":"Nitin Pundir, Noor Ahmad Hazari, Fathi H. Amsaad, M. Niamat","doi":"10.1109/NAECON.2017.8268749","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268749","url":null,"abstract":"In this paper, machine learning attacks are performed on a novel hybrid delay based Arbiter Ring Oscillator PUF (AROPUF). The AROPUF exhibits improved results when compared to traditional Arbiter Physical Unclonable Function (APUF). The challenge-response pairs (CRPs) from both PUFs are fed to the multilayered perceptron model (MLP) with one hidden layer. The results show that the CRPs generated from the proposed AROPUF has more training and prediction errors when compared to the APUF, thus making it more difficult for the adversary to predict the CRPs.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126630279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-27DOI: 10.1109/NAECON.2017.8268745
Khaled Alrawashdeh, C. Purdy
Deep learning algorithms produced impressive results in the image and voice recognition fields. Machine learning approach can be implemented to improve anomaly detection method to detect novel attacks. We use dynamic fixed-point arithmetic to reduce Deep Belief Network (DBN) calculations in an FPGA. We trained a three-layer DBN using contrastive divergence with pipeline structure, fine-tuning the network using a softmax function. Our work using dynamic fixed-point arithmetic and pipeline structure reduced the calculation requirement of the DBN more than 30% compare to the 16-bit implementation. We used the MNIST dataset for evaluation before testing online intrusion detection and achieved accuracy of 94.6% on the NSL-KDD dataset and 95.1% on the HTTP CSIC 2010 dataset. We produced efficient resource utilization and detection speed of .008ms. Our design can be further improved to decrease deep learning resources during training and testing for online intrusion detection in low powered devices.
{"title":"Reducing calculation requirements in FPGA implementation of deep learning algorithms for online anomaly intrusion detection","authors":"Khaled Alrawashdeh, C. Purdy","doi":"10.1109/NAECON.2017.8268745","DOIUrl":"https://doi.org/10.1109/NAECON.2017.8268745","url":null,"abstract":"Deep learning algorithms produced impressive results in the image and voice recognition fields. Machine learning approach can be implemented to improve anomaly detection method to detect novel attacks. We use dynamic fixed-point arithmetic to reduce Deep Belief Network (DBN) calculations in an FPGA. We trained a three-layer DBN using contrastive divergence with pipeline structure, fine-tuning the network using a softmax function. Our work using dynamic fixed-point arithmetic and pipeline structure reduced the calculation requirement of the DBN more than 30% compare to the 16-bit implementation. We used the MNIST dataset for evaluation before testing online intrusion detection and achieved accuracy of 94.6% on the NSL-KDD dataset and 95.1% on the HTTP CSIC 2010 dataset. We produced efficient resource utilization and detection speed of .008ms. Our design can be further improved to decrease deep learning resources during training and testing for online intrusion detection in low powered devices.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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