W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell
{"title":"PANDA-a hierarchical mixed mode VLSI module assembler","authors":"W.R. Bullman, L.A. Davieau, H. Moscovitz, G. O'Donnell","doi":"10.1109/CICC.1989.56820","DOIUrl":null,"url":null,"abstract":"A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A description is given of PANDA, a hierarchical, constraint-based mixed-mode VLSI module assembler. PANDA was developed as a testbed for exploring VLSI design methods and tools. It uses pitchmatching and abutment as the primary assembly technique with channel and river routers available as options. PANDA features a recursive compaction algorithm using depth-first searching, constraint resolution, and wire-length minimization to optimize layout area, while maintaining the input hierarchy. Instead of using a predetermined stand-off distance between cells, PANDA's abutment algorithm calculates the minimum distance required to guarantee no design-rule errors between modules. PANDA has the unique ability to assemble mixed-mode layouts, which are defined as a mixture of fixed-grid cells, such as hand layouts, and symbolic cells (virtual-grid), and places few constraints on the hierarchical description. Hierarchical models of over 70 K transistors have been assembled with layout densities as good as or better than achieved with hand layout