Power grid analysis on parallel computing platforms

Abstract

Due to extremely large size of power grid networks, the realistic simulation of VLSI power distribution network (power grid analysis) is computationally intensive both in terms of runtime and memory. The ongoing trends in technology scaling imply to design fast and power efficient circuits. With smaller feature sizes and variability in silicon, it has become a challenging task to design and analyze a reliable power distribution network inside a chip for correct logical functioning of an electronic circuit. In order to analyze a power grid network accurately and efficiently, a suitable computing environment and a correct technique need to be adopted. This work presents a parallel technique based on random walk algorithm using parallel computing environments like Intel Xeon Phi and Graphics Processing Unit. The proposed method has shown speedup of 55 and 67 folds as compared to its sequential version while analyzing a power grid network having 25 million nodes on Intel Xeon Phi co-processor and Graphics Processing Unit (GPU) respectively.