Substrate Effects in GaN-on-Si Integrated Bridge Circuit and Proposal of Engineered Bulk Silicon Substrate for GaN Power ICs

Abstract

In this work, the substrate effects in GaN-on-Si power ICs are systematically investigated, and a novel GaN power IC platform on engineered bulk silicon substrate is proposed to effectively address these negative effects. For the GaN-on-Si power ICs, the integrated high-side (HS-) transistor and low-side (LS-) transistor have to share a common conductive silicon substrate. The termination of the substrate cannot be optimized for both the HS- and LS-transistors, so one of the transistors has to suffer a significant degradation in the dynamic RON. The proposed engineered bulk silicon substrate provides a common mechanical substrate for both the HS- and LS-transistors. For each of the transistors, the engineered substrate also provides a localized electrical substrate region. The electrical substrate region is isolated from the mechanical substrate by a reversely biased PN junction. TCAD simulations show that the substrate effects are completely eliminated in the novel GaN power IC on engineered bulk silicon substrate.