{"title":"Using VHDL for HW/SW co-specification","authors":"W. Ecker","doi":"10.1109/EURDAC.1993.410683","DOIUrl":null,"url":null,"abstract":"HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design where it is mostly used at the RT level. VHDL implementations of abstract data and control structures which support clock independent communication and synchronization allow one to extend VHDL toward system level and HW/SW co-design.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410683","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 29

Abstract

HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design where it is mostly used at the RT level. VHDL implementations of abstract data and control structures which support clock independent communication and synchronization allow one to extend VHDL toward system level and HW/SW co-design.<>
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
使用VHDL实现硬件/软件协同规范
HW/SW(硬件/软件)协同规范和协同设计需要一种媒介来独立描述HW/SW实现以及硬件和软件的集成。由于并非所有设计步骤都可以自动执行,因此该媒介必须能够表示来自CAD工具和人类交互的中间设计步骤的结果。VHDL在硬件设计中被广泛接受,它主要用于RT级别。支持与时钟无关的通信和同步的抽象数据和控制结构的VHDL实现允许将VHDL扩展到系统级和硬件/软件协同设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Conditional and unconditional hardware sharing in pipeline synthesis Partitioning strategies within a distributed multilevel logic simulator including dynamic repartitioning Extended 0/1 LP formulation for the scheduling problem in high-level synthesis The CALLAS synthesis system and its application to mechatronic ASIC design problems Realizing expression graphs using table-lookup FPGAs
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1