Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino
{"title":"Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing","authors":"Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino","doi":"10.1109/CICC.2007.4405728","DOIUrl":null,"url":null,"abstract":"In this paper, we propose the novel architecture of VCLD (via configurable logic device) called VPEX (via programmable logic using exclusive-OR array) which is optimized for electron beam (EB) direct writing. The logic element (LE) of VPEX consists of complex gate type exclusive OR (EXOR) and inverter (NOT) gates. The single LE can output 12 logics which include all 2-inputs logic functions (NAND, NOR AND, OR bubble AND, bubble OR XOR XNOR), 3 inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout. Scan D-FlipFlop can be composed by using 5 LEs. The logic of each LE can be defined by double EB exposure using \"character beam\". The speed performance of VPEX is much better than that of FPGAs, and 1.5 times worse than that of ASICs. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we propose the novel architecture of VCLD (via configurable logic device) called VPEX (via programmable logic using exclusive-OR array) which is optimized for electron beam (EB) direct writing. The logic element (LE) of VPEX consists of complex gate type exclusive OR (EXOR) and inverter (NOT) gates. The single LE can output 12 logics which include all 2-inputs logic functions (NAND, NOR AND, OR bubble AND, bubble OR XOR XNOR), 3 inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout. Scan D-FlipFlop can be composed by using 5 LEs. The logic of each LE can be defined by double EB exposure using "character beam". The speed performance of VPEX is much better than that of FPGAs, and 1.5 times worse than that of ASICs. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.