A triple metal interconnection process for CMOS technology

Abstract

A triple interconnection process suitable for a CMOS 1.2- mu m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P/sub 2/O/sub 5/ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively.<>