A planarization technique utilizing in situ etching of TEOS-based CVD oxide is presented. The process includes TEOS/O/sub 2/-based PECVD oxide, TEOS/O/sub 3/-based LPCVD oxide, Ar/sup +/ sputter etching, and CF/sub 4/-based reactive ion etching, all in a single pumpdown. This planarization process has been successfully used to fabricate advanced double-poly double-metal circuits on 0.8- mu m CMOS technologies. E-test structures indicate low via resistance (0.15 Omega /via) and the absence of any metal opens or shorts. Custom-designed defect monitors show extremely low defect densities for both vias and metal. Comparison of die yields for the new in situ TEOS-etchback process and an SOG-etchback process indicates that much higher yields can be obtained by the use of the new process.<>
{"title":"A single-pass, in-situ planarization process utilizing TEOS for double-poly, double-metal CMOS technologies","authors":"S. Mehta, G. Sharma","doi":"10.1109/VMIC.1989.78009","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78009","url":null,"abstract":"A planarization technique utilizing in situ etching of TEOS-based CVD oxide is presented. The process includes TEOS/O/sub 2/-based PECVD oxide, TEOS/O/sub 3/-based LPCVD oxide, Ar/sup +/ sputter etching, and CF/sub 4/-based reactive ion etching, all in a single pumpdown. This planarization process has been successfully used to fabricate advanced double-poly double-metal circuits on 0.8- mu m CMOS technologies. E-test structures indicate low via resistance (0.15 Omega /via) and the absence of any metal opens or shorts. Custom-designed defect monitors show extremely low defect densities for both vias and metal. Comparison of die yields for the new in situ TEOS-etchback process and an SOG-etchback process indicates that much higher yields can be obtained by the use of the new process.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114651150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Loss and dispersion characteristics have been investigated for narrow-linewidth 5- mu m- and 1- mu m-wide Au/Cr microstrip structures on low- and high-resistivity semiconductor substrates. Low-resistivity silicon substrates with narrow microstrip lines exhibit large losses and moderate-to-excessive dispersion, which may render them undesirable for use in large-area, high-speed, VLSI circuits. Alternatively, high-resistivity silicon substrates were found to have significantly lower attenuation and nearly linear phase characteristics for 5- mu m linewidths over the 10-GHz frequency range considered. However, for 1- mu m linewidths the loss and dispersion characteristics for both high- and low-resistivity substrate microstrip lines may be problematic when used in digital and analog environments where maintaining waveform integrity is of key concern. The data presented should assist in the design and layout of high-speed, large VLSI chips which use small geometry interconnects.<>
{"title":"Transmission characteristics of narrow line-width interconnections on silicon substrates","authors":"C. J. Scott","doi":"10.1109/VMIC.1989.78004","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78004","url":null,"abstract":"Loss and dispersion characteristics have been investigated for narrow-linewidth 5- mu m- and 1- mu m-wide Au/Cr microstrip structures on low- and high-resistivity semiconductor substrates. Low-resistivity silicon substrates with narrow microstrip lines exhibit large losses and moderate-to-excessive dispersion, which may render them undesirable for use in large-area, high-speed, VLSI circuits. Alternatively, high-resistivity silicon substrates were found to have significantly lower attenuation and nearly linear phase characteristics for 5- mu m linewidths over the 10-GHz frequency range considered. However, for 1- mu m linewidths the loss and dispersion characteristics for both high- and low-resistivity substrate microstrip lines may be problematic when used in digital and analog environments where maintaining waveform integrity is of key concern. The data presented should assist in the design and layout of high-speed, large VLSI chips which use small geometry interconnects.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Joshi, S. Brodsky, T. Bucelot, M. Jaso, R. Uttecht
The most critical issues of interfacial contact between CVD (chemical vapor deposition) W and Al-Cu-Si in submicron vias using SiH/sub 4/ and H/sub 2/ reduction of WF/sub 6/ are addressed. The effect of process parameters of selective CVD W, especially when deposited by SiH/sub 4/-based chemistry, on contact resistance to Al-Cu-Si is evaluated for the first time. It is observed that out of all process parameters the deposition temperature affects the contact resistance the most. As the deposition temperature increases, the contact resistance of the stack W/Al-Cu-Si decreases. Specific resistivities, as low as 3-5*10/sup -9/ Omega cm/sup 2/, are realized at turret temperatures of 550 degrees C. On the other hand, the contact resistances are relatively unaffected by partial pressures of SiH/sub 4/ or WF/sub 6/. As a result the growth rates which are dependent on partial pressures do not control the contact resistances. Phosphoric-chromic and buffered hydrofluoric acid cleanings combined with higher deposition temperatures yield relatively superior contact resistance compared to other cleaning techniques.<>
{"title":"Low-resistance submicron CVD W interlevel via plugs on Al-Cu-Si","authors":"R. Joshi, S. Brodsky, T. Bucelot, M. Jaso, R. Uttecht","doi":"10.1109/VMIC.1989.78013","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78013","url":null,"abstract":"The most critical issues of interfacial contact between CVD (chemical vapor deposition) W and Al-Cu-Si in submicron vias using SiH/sub 4/ and H/sub 2/ reduction of WF/sub 6/ are addressed. The effect of process parameters of selective CVD W, especially when deposited by SiH/sub 4/-based chemistry, on contact resistance to Al-Cu-Si is evaluated for the first time. It is observed that out of all process parameters the deposition temperature affects the contact resistance the most. As the deposition temperature increases, the contact resistance of the stack W/Al-Cu-Si decreases. Specific resistivities, as low as 3-5*10/sup -9/ Omega cm/sup 2/, are realized at turret temperatures of 550 degrees C. On the other hand, the contact resistances are relatively unaffected by partial pressures of SiH/sub 4/ or WF/sub 6/. As a result the growth rates which are dependent on partial pressures do not control the contact resistances. Phosphoric-chromic and buffered hydrofluoric acid cleanings combined with higher deposition temperatures yield relatively superior contact resistance compared to other cleaning techniques.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<>
{"title":"An improved interlevel dielectric process for submicron double-level metal products","authors":"S. Pennington, S. Luce, D.P. Hallock","doi":"10.1109/VMIC.1989.77994","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77994","url":null,"abstract":"An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115351334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A report is presented on AlSi(1%), AlSi(1%)Ti(0.1%), and AlSi(1%)Cu(0.5%) alloy planarization results using a XeCl excimer laser. The authors find that excellent planarization is achieved when filling submicron contact hole structures. However, for the AlSi alloy, spot ablation occurs which is characterized by the removal of metal. This is not the case for the AlSiCu and the AlSiTi alloys. The best morphology is obtained for the AlSiTi alloy with large areas completely free of ablation and pitting. These results indicate that reliable planarization over large device areas can be achieved using the AlSiTi alloy.<>
{"title":"Improved excimer laser planarization of AlSi with addition of Ti or Cu","authors":"B. Woratschek, P. Carey, M. Stolz, F. Bachmann","doi":"10.1109/VMIC.1989.77989","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77989","url":null,"abstract":"A report is presented on AlSi(1%), AlSi(1%)Ti(0.1%), and AlSi(1%)Cu(0.5%) alloy planarization results using a XeCl excimer laser. The authors find that excellent planarization is achieved when filling submicron contact hole structures. However, for the AlSi alloy, spot ablation occurs which is characterized by the removal of metal. This is not the case for the AlSiCu and the AlSiTi alloys. The best morphology is obtained for the AlSiTi alloy with large areas completely free of ablation and pitting. These results indicate that reliable planarization over large device areas can be achieved using the AlSiTi alloy.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Advanced ULSI circuits require minimum features >
只提供摘要形式。先进的ULSI电路需要最小的功能
{"title":"A comparison of a two layer metal system built with selective CVD W plugs and elevated temperature, sputtered Al(Cu)","authors":"S. R. Wilson, R. J. Mattox, J. Sellers","doi":"10.1109/VMIC.1989.78047","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78047","url":null,"abstract":"Summary form only given. Advanced ULSI circuits require minimum features <or=1.0 mu m to maximize packing density. In addition, metal line pinches must be approximately 2.0 mu m and vias <or=1.0 mu m with straight walls. Thicker interlevel dielectrics for capacitance reduction mean that the aspect ratio (height/width) of vias must be approximately 1.0. These high aspect ratios greatly reduce the step coverage of sputtered metal causing two potential problems: (1) increased via resistance and (2) sources of reliability failure. To study these issues, the authors used a double-level metal vehicle with a range of metal 1 pitch of 1.75-3.0 mu m, a metal 2 pitch range of 3.0-4.5 mu m, and a range of via sizes from (0.75 mu m)/sup 2/ to (1.5 mu m)/sup 2/. The via chains using W to achieve an approximately 100% via fill had excellent results. All chains were continuous and the average resistance/via was 0.33, 0.19 and 0.13 Omega for the (0.75 mu m)/sup 2/, (1.0 mu m)/sup 2/, and (1.25 mu m)/sup 2/ via chains, respectively. The standard deviation across a wafer in each case was less than 2%. When the Wfills were 75% on the smallest vias the step coverage from 325 degrees C sputtered AlCu was poor; causing some opens and an increase in the mean and standard deviation of the Omega /via. On larger vias with same percent fill, the chains were continuous, but the resistance was greater than for the 100% fills. This is an issue when the vias have different depths due to underlying topography.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen
The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<>
最终钝化层影响器件的电气行为，也影响器件、封装和产品可靠性中的各种失效机制，因为它与下面的金属层和上面的封装材料相互作用。为了解决所涉及的各种问题，对几种钝化方案进行了评价。提出了一种将PECVD- teos与其他PECVD膜结合用于0.7 μ m和0.5 μ m CMOS SRAM工艺的方案。
{"title":"Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films","authors":"W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen","doi":"10.1109/VMIC.1989.77995","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77995","url":null,"abstract":"The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130345931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Kamgar, R. Knoell, F. Baiocchi, K. Orlowsky, K. Cheung, R. Liu
The integrity of Al/barrier/CoSi/sub 2/ junctions subjected to Al melting was studied. Melting was accomplished by irradiating Si wafers in a rapid thermal anneal system. Three types of barrier were studied: TiN, W:Ti, and a bilayer of W:Ti/TiN. Junction leakage measurements indicated that the W:Ti/TiN bilayer was superior to the other two and that it withstood temperatures at least 60 degrees C higher than the Al melting temperature for one second or less. Rutherford backscattering, X-ray diffraction, and etchback experiments were performed to determine the extent of interaction between the various layers after the melt. The authors found that for the W:Ti barrier, upon melting of Al, W reacted readily with Al and Si, forming the ternary alloy, W(Al,Si)/sub 2/, and possibly other phases including Co as a constituent. TiN on the other hand effectively prevented the reaction of Al and W with Co and Si.<>
{"title":"Impact of Al melting on diode integrity","authors":"A. Kamgar, R. Knoell, F. Baiocchi, K. Orlowsky, K. Cheung, R. Liu","doi":"10.1109/VMIC.1989.78022","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78022","url":null,"abstract":"The integrity of Al/barrier/CoSi/sub 2/ junctions subjected to Al melting was studied. Melting was accomplished by irradiating Si wafers in a rapid thermal anneal system. Three types of barrier were studied: TiN, W:Ti, and a bilayer of W:Ti/TiN. Junction leakage measurements indicated that the W:Ti/TiN bilayer was superior to the other two and that it withstood temperatures at least 60 degrees C higher than the Al melting temperature for one second or less. Rutherford backscattering, X-ray diffraction, and etchback experiments were performed to determine the extent of interaction between the various layers after the melt. The authors found that for the W:Ti barrier, upon melting of Al, W reacted readily with Al and Si, forming the ternary alloy, W(Al,Si)/sub 2/, and possibly other phases including Co as a constituent. TiN on the other hand effectively prevented the reaction of Al and W with Co and Si.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Via electromigration (EM) performance of Ti/W/Al-Cu(2%) metallization is reported for 1.2- mu m vias defined in 1.0 mu m of interlevel oxide. Using a Kelvin-contact stressing structure, the via resistance was monitored independently of the EM-induced damage which occurs in the metal leads servicing the via. Even for EM-induced resistance rises of up to 270% in the metal leads, the vias remained stable with via resistance rises of less than 20%. This indicates that the metal stripes exhibit electromigration wearout well before the vias fail. These results were independent of the direction of current flow in the via.<>
{"title":"Via electromigration performance of Ti/W/Al-Cu(2%) multilayered metallization","authors":"C. Martin, J. McPherson","doi":"10.1109/VMIC.1989.78063","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78063","url":null,"abstract":"Via electromigration (EM) performance of Ti/W/Al-Cu(2%) metallization is reported for 1.2- mu m vias defined in 1.0 mu m of interlevel oxide. Using a Kelvin-contact stressing structure, the via resistance was monitored independently of the EM-induced damage which occurs in the metal leads servicing the via. Even for EM-induced resistance rises of up to 270% in the metal leads, the vias remained stable with via resistance rises of less than 20%. This indicates that the metal stripes exhibit electromigration wearout well before the vias fail. These results were independent of the direction of current flow in the via.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121708981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The authors have developed a transient mathematical model incorporating simultaneous Knudsen diffusion and the competing heterogeneous reactions in rectangular trenches to predict quantitatively step coverage in tetraethylorthosilicate (TEOS) PECVD. The model reveals that deposition uniformity, and hence the step coverage, is controlled by two dimensionless groups. The first group represents a ratio of a characteristic deposition rate to a characteristic atomic oxygen diffusion rate. The second group represents the ratio of a characteristic wall recombination, or quench rate to diffusion rate. These groups can be used as a guideline to determine how process conditions should be adjusted to increase deposition rate without degrading step coverage. The model correctly predicts that high step coverages are obtained with low RF power, low pressure, and low wafer temperature.<>
{"title":"Step coverage prediction in plasma-enhanced deposition of silicon dioxide from TEOS","authors":"G. Raupp, T. Cale, H. Hey","doi":"10.1109/VMIC.1989.78042","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78042","url":null,"abstract":"Summary form only given. The authors have developed a transient mathematical model incorporating simultaneous Knudsen diffusion and the competing heterogeneous reactions in rectangular trenches to predict quantitatively step coverage in tetraethylorthosilicate (TEOS) PECVD. The model reveals that deposition uniformity, and hence the step coverage, is controlled by two dimensionless groups. The first group represents a ratio of a characteristic deposition rate to a characteristic atomic oxygen diffusion rate. The second group represents the ratio of a characteristic wall recombination, or quench rate to diffusion rate. These groups can be used as a guideline to determine how process conditions should be adjusted to increase deposition rate without degrading step coverage. The model correctly predicts that high step coverages are obtained with low RF power, low pressure, and low wafer temperature.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126308689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：