D. Byeon, Chiweon Yoon, H. Park, Yong-Kyu Lee, Hyojin Kwon, Yeong-Taek Lee, KiSeung Kim, Yong-Yeon Joo, I. Baek, Young-Bae Kim, Jehyun Choi, K. Kyung, Jeong-Hyuk Choi
{"title":"Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory","authors":"D. Byeon, Chiweon Yoon, H. Park, Yong-Kyu Lee, Hyojin Kwon, Yeong-Taek Lee, KiSeung Kim, Yong-Yeon Joo, I. Baek, Young-Bae Kim, Jehyun Choi, K. Kyung, Jeong-Hyuk Choi","doi":"10.1109/NVMTS.2014.7060837","DOIUrl":null,"url":null,"abstract":"In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2014.7060837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.