Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060854
J. Feng, Xiaorong Chen, Du-han Bae
Enough Roff/Ron ratio is important for RRAM application. In this study, a Ta2O5-α/TaOy/TaOx tri-layer structure device was fabricated by reactive sputtering and plasma oxidation and a Ta2O5-α/TaOx bi-layer structure device was also fabricated for comparison. Resistive switching characteristics of both types of devices were investigated under different compliance current. Both types of devices revealed nearly the same reset current which was as low as ~40 μA. The Roff/Ron ratio of the tri-layer structure devices was increased from 2 to more than 20 by inserting a TaOy layer. The memory windows of the bi-layer structure devices increased to 3 while the memory windows of the tri-layer structure devices decreased to 8 when the compliance current increased from 40 μA to 60 μA. The stability of the tri-layer structure devices became worse under larger compliance current. The results indicate that that inserting a TaOy is beneficial for the memory windows of devices and a smaller compliance current is more suitable for the tri-layer structure devices.
{"title":"Resistive switches in Ta2O5-α/TaO2−x Bilayer and Ta2O5-α/TaO2−x/TaO2−y Tri-layer Structures","authors":"J. Feng, Xiaorong Chen, Du-han Bae","doi":"10.1109/NVMTS.2014.7060854","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060854","url":null,"abstract":"Enough R<sub>off</sub>/R<sub>on</sub> ratio is important for RRAM application. In this study, a Ta<sub>2</sub>O<sub>5-α</sub>/TaO<sub>y</sub>/TaO<sub>x</sub> tri-layer structure device was fabricated by reactive sputtering and plasma oxidation and a Ta<sub>2</sub>O<sub>5-α</sub>/TaO<sub>x</sub> bi-layer structure device was also fabricated for comparison. Resistive switching characteristics of both types of devices were investigated under different compliance current. Both types of devices revealed nearly the same reset current which was as low as ~40 μA. The R<sub>off</sub>/R<sub>on</sub> ratio of the tri-layer structure devices was increased from 2 to more than 20 by inserting a TaO<sub>y</sub> layer. The memory windows of the bi-layer structure devices increased to 3 while the memory windows of the tri-layer structure devices decreased to 8 when the compliance current increased from 40 μA to 60 μA. The stability of the tri-layer structure devices became worse under larger compliance current. The results indicate that that inserting a TaO<sub>y</sub> is beneficial for the memory windows of devices and a smaller compliance current is more suitable for the tri-layer structure devices.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060837
D. Byeon, Chiweon Yoon, H. Park, Yong-Kyu Lee, Hyojin Kwon, Yeong-Taek Lee, KiSeung Kim, Yong-Yeon Joo, I. Baek, Young-Bae Kim, Jehyun Choi, K. Kyung, Jeong-Hyuk Choi
In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.
{"title":"Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory","authors":"D. Byeon, Chiweon Yoon, H. Park, Yong-Kyu Lee, Hyojin Kwon, Yeong-Taek Lee, KiSeung Kim, Yong-Yeon Joo, I. Baek, Young-Bae Kim, Jehyun Choi, K. Kyung, Jeong-Hyuk Choi","doi":"10.1109/NVMTS.2014.7060837","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060837","url":null,"abstract":"In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060867
G. Piccolboni, G. Molas, C. Carabasse, J. Nodin, C. Pellissier, P. Brianceau, E. Vianello, O. Pollet, F. Perrin, J. Cluzel, A. Toffoli, F. Aussenac, V. Delaye, G. Ghibaudo, B. De Salvo, L. Perniola
An easy-to-fabricate, low-cost, sidewall TiN/HfO2/Ti vertical resistive RAM (VRRAM) device is proposed. Devices with bottom electrode thickness down to 10nm were fabricated and characterized. Forming, SET and RESET voltages of respectively 2V, 0.5V and -0.5V were measured. A stable memory window of one decade was maintained after 105s at 200°C. The impact of scaling on the operating voltages and memory resistance levels was evaluated, showing a SET and RESET voltage reduction as the cell diameter is reduced. Finally the cycle-to-cycle resistance variability was addressed.
{"title":"Investigation of HfO2/Ti based vertical RRAM - Performances and variability","authors":"G. Piccolboni, G. Molas, C. Carabasse, J. Nodin, C. Pellissier, P. Brianceau, E. Vianello, O. Pollet, F. Perrin, J. Cluzel, A. Toffoli, F. Aussenac, V. Delaye, G. Ghibaudo, B. De Salvo, L. Perniola","doi":"10.1109/NVMTS.2014.7060867","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060867","url":null,"abstract":"An easy-to-fabricate, low-cost, sidewall TiN/HfO2/Ti vertical resistive RAM (VRRAM) device is proposed. Devices with bottom electrode thickness down to 10nm were fabricated and characterized. Forming, SET and RESET voltages of respectively 2V, 0.5V and -0.5V were measured. A stable memory window of one decade was maintained after 105s at 200°C. The impact of scaling on the operating voltages and memory resistance levels was evaluated, showing a SET and RESET voltage reduction as the cell diameter is reduced. Finally the cycle-to-cycle resistance variability was addressed.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060856
Patryk Skoncej
Emerging non-volatile memories such as PCRAMs, MRAMs/STT-MRAMs, FRAMs, and RRAMs are promising candidates for embedded memories in upcoming digital systems. Due to their non-volatility, low-power consumption, and scalability potential, they are best suited in applications like smartphones, tablets, wearable electronics, and sensor nodes. Unfortunately, despite all advantages they offer, emerging non-volatile memories pose some peculiar characteristics like limited endurance and/or variable data retention time. This paper proposes repair mechanism based on a well-known SEC-DED code which can significantly increase the reliability of embedded non-volatile memories.
{"title":"ECC with increased hard error correction capability for memory reliability improvement","authors":"Patryk Skoncej","doi":"10.1109/NVMTS.2014.7060856","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060856","url":null,"abstract":"Emerging non-volatile memories such as PCRAMs, MRAMs/STT-MRAMs, FRAMs, and RRAMs are promising candidates for embedded memories in upcoming digital systems. Due to their non-volatility, low-power consumption, and scalability potential, they are best suited in applications like smartphones, tablets, wearable electronics, and sensor nodes. Unfortunately, despite all advantages they offer, emerging non-volatile memories pose some peculiar characteristics like limited endurance and/or variable data retention time. This paper proposes repair mechanism based on a well-known SEC-DED code which can significantly increase the reliability of embedded non-volatile memories.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128383366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060850
F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola
In this paper, a comprehensive investigation of programming conditions in an oxide-based CBRAM device is presented. 1T-1R devices (both isolated and in a 8×8 matrix) are electrically characterized in a range of logic compatible programming conditions. Starting from the electrical results, programming conditions optimizing the memory window (ROFF/RON>25 in the worst case) and the resistance variability are identified. A corner approach is presented to fully calibrate a CBRAM compact model. The model has been implemented into an electrical simulator to assess performances of NVFF and memory circuit.
{"title":"CBRAM corner analysis for robust design solutions","authors":"F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola","doi":"10.1109/NVMTS.2014.7060850","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060850","url":null,"abstract":"In this paper, a comprehensive investigation of programming conditions in an oxide-based CBRAM device is presented. 1T-1R devices (both isolated and in a 8×8 matrix) are electrically characterized in a range of logic compatible programming conditions. Starting from the electrical results, programming conditions optimizing the memory window (ROFF/RON>25 in the worst case) and the resistance variability are identified. A corner approach is presented to fully calibrate a CBRAM compact model. The model has been implemented into an electrical simulator to assess performances of NVFF and memory circuit.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060866
Sanghyeon Lee, Gwihyun Kim, Seungwoo Hong, S. Baik, Hideki Hori, D. Ahn
Based on field induced atomic migration, one of the cycling endurance failure mechanisms in phase change memories, we propose an electrical treatment method to reduce atomic migration. The electric treatment is performed by applying compensation voltage after set or reset voltage applications, and we have a substantial enhancement of cycling endurance characteristics. The polarity of the compensation voltage is negative with respect to the programming voltages. To further investigate the effect of the electrical treatment, we introduced a parameter named melting voltage, which steadily increases as the number of set/reset cycling increases. This observation is consistent with the increase of resistance at the reset voltage, which supports void formation in the active region of Ge2Sb2Te5 with cycling stress.
{"title":"Enhanced cycling endurance in phase change memory via electrical control of switching induced atomic migration","authors":"Sanghyeon Lee, Gwihyun Kim, Seungwoo Hong, S. Baik, Hideki Hori, D. Ahn","doi":"10.1109/NVMTS.2014.7060866","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060866","url":null,"abstract":"Based on field induced atomic migration, one of the cycling endurance failure mechanisms in phase change memories, we propose an electrical treatment method to reduce atomic migration. The electric treatment is performed by applying compensation voltage after set or reset voltage applications, and we have a substantial enhancement of cycling endurance characteristics. The polarity of the compensation voltage is negative with respect to the programming voltages. To further investigate the effect of the electrical treatment, we introduced a parameter named melting voltage, which steadily increases as the number of set/reset cycling increases. This observation is consistent with the increase of resistance at the reset voltage, which supports void formation in the active region of Ge2Sb2Te5 with cycling stress.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060865
C. Tanaka, K. Abe, H. Noguchi, K. Nomura, K. Ikegami, S. Fujita
This paper describes a scaling of MRAM cell area with advanced high performance CMOS technology. The cell area scalability for the cache memory considering MTJ resistivity, switching current, and drive current of access transistor are demonstrated. We consider the layout that the gate pitches are pinned at 3F to 4F. In order to minimize MRAM cell area, it indicates that MTJ resistivity and switching current are the most important factor. Novel scalability of memory cell size with CMOS technology node can be performed with advanced MTJ technology.
{"title":"A scaling of cell area with perpendicular STT-MRAM cells as an embedded memory","authors":"C. Tanaka, K. Abe, H. Noguchi, K. Nomura, K. Ikegami, S. Fujita","doi":"10.1109/NVMTS.2014.7060865","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060865","url":null,"abstract":"This paper describes a scaling of MRAM cell area with advanced high performance CMOS technology. The cell area scalability for the cache memory considering MTJ resistivity, switching current, and drive current of access transistor are demonstrated. We consider the layout that the gate pitches are pinned at 3F to 4F. In order to minimize MRAM cell area, it indicates that MTJ resistivity and switching current are the most important factor. Novel scalability of memory cell size with CMOS technology node can be performed with advanced MTJ technology.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126338974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060835
N. Takaura, T. Ohyanagi, M. Tai, T. Morikawa, M. Kinoshita, K. Akita
The fabrication of topological-switching random-access memory (TRAM), a new type of phase change memory, was investigated. The deposition and etching process technologies of a GeTe/Sb2Te3 superlattice memory cell were developed and micro test structures of TRAM were fabricated. Analysis of the fabricated structures revealed that the electrical properties of TRAM were different from those of conventional phase change memory and the reset voltage of TRAM, 0.6 V, was less than that of PRAM, 1 V. The non-melting behaviors of resistance change in TRAM were clarified via thermal-conductivity measurements and device simulation.
{"title":"Fabrication of topological-switching RAM (TRAM)","authors":"N. Takaura, T. Ohyanagi, M. Tai, T. Morikawa, M. Kinoshita, K. Akita","doi":"10.1109/NVMTS.2014.7060835","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060835","url":null,"abstract":"The fabrication of topological-switching random-access memory (TRAM), a new type of phase change memory, was investigated. The deposition and etching process technologies of a GeTe/Sb2Te3 superlattice memory cell were developed and micro test structures of TRAM were fabricated. Analysis of the fabricated structures revealed that the electrical properties of TRAM were different from those of conventional phase change memory and the reset voltage of TRAM, 0.6 V, was less than that of PRAM, 1 V. The non-melting behaviors of resistance change in TRAM were clarified via thermal-conductivity measurements and device simulation.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060863
R. Mandapati, B. Das, V. Ostwal, U. Ganguly
In this paper, first we evaluate array power performance using both Voltage Designable (VD) and Non-Voltage Designable (NVD) selection device (1S) technologies for (a) compatibility with range of memory (1M) operating voltages and currents and (b) selector variability. Firstly, cross-point (1S1M) on-off ratio degrades exponentially with NVD selectors for higher memory voltages while VD selectors provide immunity from such degradation by designing (increasing) the selector voltage. Consequently, array power increases exponentially for NVD selectors for higher memory voltages while it can be controlled effectively using VD selectors. Secondly, selector variability causes a necessary increase in cross-point voltage to ensure that majority (>99%) of the cross-points can be programmed. We show that selector variability also increases total array leakage (i.e Ioff). Designability of selector voltage available in VD selector enables the immunity from array power increase due to selector variability. Thus, VD selector is attractive due to its broad memory technology compatibility and selector variability immunity.
{"title":"Voltage Designability: An enabler for selector technology","authors":"R. Mandapati, B. Das, V. Ostwal, U. Ganguly","doi":"10.1109/NVMTS.2014.7060863","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060863","url":null,"abstract":"In this paper, first we evaluate array power performance using both Voltage Designable (VD) and Non-Voltage Designable (NVD) selection device (1S) technologies for (a) compatibility with range of memory (1M) operating voltages and currents and (b) selector variability. Firstly, cross-point (1S1M) on-off ratio degrades exponentially with NVD selectors for higher memory voltages while VD selectors provide immunity from such degradation by designing (increasing) the selector voltage. Consequently, array power increases exponentially for NVD selectors for higher memory voltages while it can be controlled effectively using VD selectors. Secondly, selector variability causes a necessary increase in cross-point voltage to ensure that majority (>99%) of the cross-points can be programmed. We show that selector variability also increases total array leakage (i.e Ioff). Designability of selector voltage available in VD selector enables the immunity from array power increase due to selector variability. Thus, VD selector is attractive due to its broad memory technology compatibility and selector variability immunity.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117238461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060852
Jeongsu Lee, Gunwoo Lee, O. Sul, Seung-Beck Lee
Analytical simulations are performed to investigate effects of pass gate bias (Vpass) and vertical pitch scaling on a 3D silicon-oxide-nitride-oxide-silicon (SONOS) NAND Flash string. Maximum programmed threshold voltage (VT) degradation and severe cell-to-cell interference were found as the two vertical length parameters-the gate length (LG) and the inter-layer dielectric length (LILD)-are scaled. Detailed quantitative numerical simulations revealed that the increased electric field between the adjacent memory cells is the main cause for those aforementioned results. Finally, minimum scalable cell-to-cell distance was found in terms of cell-to-cell leakage current. These results will give an allowable vertical scaling margin to the 3-D stacked cylindrical memories.
{"title":"Effects of Vpass and vertical pitch on 3D SONOS NAND Flash memory operations","authors":"Jeongsu Lee, Gunwoo Lee, O. Sul, Seung-Beck Lee","doi":"10.1109/NVMTS.2014.7060852","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060852","url":null,"abstract":"Analytical simulations are performed to investigate effects of pass gate bias (Vpass) and vertical pitch scaling on a 3D silicon-oxide-nitride-oxide-silicon (SONOS) NAND Flash string. Maximum programmed threshold voltage (VT) degradation and severe cell-to-cell interference were found as the two vertical length parameters-the gate length (LG) and the inter-layer dielectric length (LILD)-are scaled. Detailed quantitative numerical simulations revealed that the increased electric field between the adjacent memory cells is the main cause for those aforementioned results. Finally, minimum scalable cell-to-cell distance was found in terms of cell-to-cell leakage current. These results will give an allowable vertical scaling margin to the 3-D stacked cylindrical memories.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116301927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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