A distributed BIST architecture enabling extended sharing and debug capabilities

Abstract

This paper presents a new distributed built in self test architecture for multiple embedded memories. This architecture has the specificity to address simultaneously two of the most challenging aspects: parallel at-speed testing and extended diagnosis capabilities. The latter feature allows debug for prototypes and yield enhancement at production level. Proposed architecture is optimized for March algorithms, taking advantage from their hierarchical and regular structure in order to minimize interconnect and area overhead