Simulation and modeling of a multicast ATM switch

Abstract

This article presents the core design of a high-speed [8 Gbps] nonblocking multicast ATM cell switch. The switch uses a self-routing ring of shift-registers to transfer cells from one port to another in a pipelined fashion resolving output contention and efficiently handling multicast cells. The "ring" architecture is advantageous from a VLSI standpoint. A novel feature of this design is an intelligent scheduler at the output buffers which provided a physical switch level support for QoS handling. This algorithm called helix-virtual-Q emulates a "Weighted-Round-Robin Scheduling" on a single-FIFO based output buffer. An object oriented high level simulation model provided key design parameters for the synthesizeable VHDL descriptions that followed.