Junction technology challenges and solutions for 3D device architecture

Abstract

Fabrication cost reduction and performance improvements of state-of-the-art complementary metal–oxide–semiconductor (CMOS) are driving force of device size scaling as well as chip size scaling. To enable continuous device scaling, the device structure was changed from planar field-effect transistors (FETs) to FinFETs shown in Fig. 1 [1] . The FinFETs have the 3D channel shown in Fig. 1 , and it increases on-state current (I on ) per footprint, and suppresses short-channel effects (SCEs) and off-state current (I off ).