Pub Date : 2019-06-06DOI: 10.23919/IWJT.2019.8802892
Y. Morita, K. Fukuda, T. Mori, T. Matsukawa
With an increase in the amount of collected and modified data in today’s "big data" era, the demand for calculation resources in both "cloud" and "edge" has also increased. Circuits consume high power when calculating large amount of data. Presently, advanced microchips consume over 100 W of power, which is a critical problem of realizing the big data/IoT/AI concepts. Reducing the operation voltage (V DD ) of devices is the most effective way to reduce power consumption of chips. The IRDS roadmap predicts ways to simultaneously reduce V DD and "subthreshold swing" (SS) [1] . However, the SS of a MOSFET is limited to 60 mV/decade at room temperature because of its operation mechanism [2] . Thus, remarkably reducing the MOSFET operating voltage is difficult. To overcome this problem, novel devices having different operation mechanisms from the MOSFET are required [3] – [5] .
{"title":"Fabrication of epitaxial tunnel junction on tunnel field effect transistors","authors":"Y. Morita, K. Fukuda, T. Mori, T. Matsukawa","doi":"10.23919/IWJT.2019.8802892","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802892","url":null,"abstract":"With an increase in the amount of collected and modified data in today’s \"big data\" era, the demand for calculation resources in both \"cloud\" and \"edge\" has also increased. Circuits consume high power when calculating large amount of data. Presently, advanced microchips consume over 100 W of power, which is a critical problem of realizing the big data/IoT/AI concepts. Reducing the operation voltage (V DD ) of devices is the most effective way to reduce power consumption of chips. The IRDS roadmap predicts ways to simultaneously reduce V DD and \"subthreshold swing\" (SS) [1] . However, the SS of a MOSFET is limited to 60 mV/decade at room temperature because of its operation mechanism [2] . Thus, remarkably reducing the MOSFET operating voltage is difficult. To overcome this problem, novel devices having different operation mechanisms from the MOSFET are required [3] – [5] .","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132528539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-06DOI: 10.23919/IWJT.2019.8802886
K. Shima, K. Kojima, A. Uedono, S. Chichibu
GaN is one of the promising candidates for the use in high-power electronic devices 1) operating at high frequencies, and normally-off GaN-based transistors on freestanding (FS) GaN substrates with low specific on-state resistances (~1.0 mΩ•cm 2) and high off-state breakdown voltage (>1.7 kV) have been demonstrated. 2 – 4) One of the challenging issues for producing such devices at low cost is the control of conductivity type and conductivity at designated segments using an ion-implantation (I/I) technique. Especially, p-type doping by Mg-I/I has been difficult 5 – 8) because donor-type defects introduced by I/I and/or donor impurities such as O or Si diffused from the protective overlayer during post-implantation annealing (PIA) 7) likely compensate holes.
{"title":"Photoluminescence Studies of Sequentially Mg and H Ion-implanted GaN with Various Implantation Depths and Crystallographic Planes","authors":"K. Shima, K. Kojima, A. Uedono, S. Chichibu","doi":"10.23919/IWJT.2019.8802886","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802886","url":null,"abstract":"GaN is one of the promising candidates for the use in high-power electronic devices 1) operating at high frequencies, and normally-off GaN-based transistors on freestanding (FS) GaN substrates with low specific on-state resistances (~1.0 mΩ•cm 2) and high off-state breakdown voltage (>1.7 kV) have been demonstrated. 2 – 4) One of the challenging issues for producing such devices at low cost is the control of conductivity type and conductivity at designated segments using an ion-implantation (I/I) technique. Especially, p-type doping by Mg-I/I has been difficult 5 – 8) because donor-type defects introduced by I/I and/or donor impurities such as O or Si diffused from the protective overlayer during post-implantation annealing (PIA) 7) likely compensate holes.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121787823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-06DOI: 10.23919/IWJT.2019.8802622
K. Matsuura, M. Hamada, T. Hamada, H. Tanigawa, T. Sakamoto, W. Cao, K. Parto, A. Hori, I. Muneta, T. Kawanago, K. Kakushima, K. Tsutsui, A. Ogura, K. Banerjee, H. Wakabayashi
We have successfully fabricated chip-level integrated nMISFETs with sputtered molybdenum disulfide (MoS2) thin channel using sulfur-powder annealing (SPA) and molybdenum disilicide (MoSi2) contact which show n-type-normally-off operation in accumulation. SPA intentionally compensated sulfur vacancies of sputtered MoS2 film. Eventually, we achieved a normally-off operation, which realizes industrial chip-level LSIs with MoS2 channel.
{"title":"Normally-Off Sputtered-MoS2 nMISFETs with MoSi2 Contact by Sulfur Powder Annealing and ALD Al2O3 Gate Dielectric for Chip Level Integration","authors":"K. Matsuura, M. Hamada, T. Hamada, H. Tanigawa, T. Sakamoto, W. Cao, K. Parto, A. Hori, I. Muneta, T. Kawanago, K. Kakushima, K. Tsutsui, A. Ogura, K. Banerjee, H. Wakabayashi","doi":"10.23919/IWJT.2019.8802622","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802622","url":null,"abstract":"We have successfully fabricated chip-level integrated nMISFETs with sputtered molybdenum disulfide (MoS2) thin channel using sulfur-powder annealing (SPA) and molybdenum disilicide (MoSi2) contact which show n-type-normally-off operation in accumulation. SPA intentionally compensated sulfur vacancies of sputtered MoS2 film. Eventually, we achieved a normally-off operation, which realizes industrial chip-level LSIs with MoS2 channel.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125565883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-06DOI: 10.23919/IWJT.2019.8802893
L. Jastrzebski, R. Duru, D. Le-Cunff, M. Cannac, S. Joblot, I. Mica, M. Polignano, A. Galbiati, P. Monge, Roffarello, G. Nadudvari, Z. Kiss, I. Lajtos, A. Pongrácz, G. Molnár, M. Nagy, L. Dudás, P. Basa, B. Greenwood, J. Gambino
As Si is an indirect band gap material, the PL generated by phonon assisted band-to-band (B2B) radiative recombination (of energy equal to energy gap of Si) is very weak; about 10 orders of magnitude lower than the exciting photon flux [1] . If crystallographic defects are present then at room temperature an additional broad defect PL peak is generated (DPL) with energy smaller than the band gap of Si [1] , [2] , [3] . At room temperature, defect-band PL intensity is orders of magnitude lower than the B2B intensity [1] .
{"title":"Review of applications of Defect Photoluminescence Imaging (DPLI) during IC processing","authors":"L. Jastrzebski, R. Duru, D. Le-Cunff, M. Cannac, S. Joblot, I. Mica, M. Polignano, A. Galbiati, P. Monge, Roffarello, G. Nadudvari, Z. Kiss, I. Lajtos, A. Pongrácz, G. Molnár, M. Nagy, L. Dudás, P. Basa, B. Greenwood, J. Gambino","doi":"10.23919/IWJT.2019.8802893","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802893","url":null,"abstract":"As Si is an indirect band gap material, the PL generated by phonon assisted band-to-band (B2B) radiative recombination (of energy equal to energy gap of Si) is very weak; about 10 orders of magnitude lower than the exciting photon flux [1] . If crystallographic defects are present then at room temperature an additional broad defect PL peak is generated (DPL) with energy smaller than the band gap of Si [1] , [2] , [3] . At room temperature, defect-band PL intensity is orders of magnitude lower than the B2B intensity [1] .","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123471073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802620
J. Liu, J. Wan
Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.
基于完全耗尽绝缘体上硅(FD-SOI)衬底的零冲击电离零亚阈值摆幅场效应管(z2 -FET)是一种电子与空穴流动正反馈机制的新型器件。它已经显示出非常锐利的开关特性，SS低至1mV/dec，开/关比高达10.8[1]，[2]。此外，z2 -FET的I - D - V - D特性和导通电压(V ON)由栅极电压(V G)线性控制，具有较大的滞后窗。这一特性已被用于单晶体管动态随机存取存储器(DRAM)应用，与传统的单晶体管一电容(1T-1C) DRAM相比，它具有更高的存取速度和更高的集成密度[3]，[4]。然而，传统的z2 -FET具有不对称结构，顶部栅极覆盖了长沟道区域。这种不对称结构不仅会导致特征尺寸的增加，而且会带来不对准，从而降低器件的性能。
{"title":"Z2-FET: Application in Image Sensing and Self-aligned Structure for Further Scaling Down","authors":"J. Liu, J. Wan","doi":"10.23919/IWJT.2019.8802620","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802620","url":null,"abstract":"Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"66 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120928144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802902
F. Gámiz, S. Navarro, C. Navarro, C. Márquez, C. Sampedro, L. Donetti, P. Galy, S. Cristoloveanu
Electrostatic doping (ED) offers an alternative to chemical doping in nanometer-scale devices. Recent works have shown the applicability of ED in a host of devices based on different materials ranging from Si and ultrahin fully depleted Silicon-on-Insulator layers to carbon nanotubes, graphene, and other 2D semiconductors, specially transition metal dichalcogenides (TMDs) [1] . In this work, we will demonstrate the application of electrostatic doping to form virtual junctions in an undoped ultrathin Silicon on Insulator layer, which can be operated as a memory device.
{"title":"Capacitorless memory devices using virtual junctions","authors":"F. Gámiz, S. Navarro, C. Navarro, C. Márquez, C. Sampedro, L. Donetti, P. Galy, S. Cristoloveanu","doi":"10.23919/IWJT.2019.8802902","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802902","url":null,"abstract":"Electrostatic doping (ED) offers an alternative to chemical doping in nanometer-scale devices. Recent works have shown the applicability of ED in a host of devices based on different materials ranging from Si and ultrahin fully depleted Silicon-on-Insulator layers to carbon nanotubes, graphene, and other 2D semiconductors, specially transition metal dichalcogenides (TMDs) [1] . In this work, we will demonstrate the application of electrostatic doping to form virtual junctions in an undoped ultrathin Silicon on Insulator layer, which can be operated as a memory device.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802891
Y. Kikuchi, H. Mertens, R. Ritzenthaler, T. Chiarella, A. Peter, N. Horiguchi
Fabrication cost reduction and performance improvements of state-of-the-art complementary metal–oxide–semiconductor (CMOS) are driving force of device size scaling as well as chip size scaling. To enable continuous device scaling, the device structure was changed from planar field-effect transistors (FETs) to FinFETs shown in Fig. 1 [1] . The FinFETs have the 3D channel shown in Fig. 1 , and it increases on-state current (I on ) per footprint, and suppresses short-channel effects (SCEs) and off-state current (I off ).
{"title":"Junction technology challenges and solutions for 3D device architecture","authors":"Y. Kikuchi, H. Mertens, R. Ritzenthaler, T. Chiarella, A. Peter, N. Horiguchi","doi":"10.23919/IWJT.2019.8802891","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802891","url":null,"abstract":"Fabrication cost reduction and performance improvements of state-of-the-art complementary metal–oxide–semiconductor (CMOS) are driving force of device size scaling as well as chip size scaling. To enable continuous device scaling, the device structure was changed from planar field-effect transistors (FETs) to FinFETs shown in Fig. 1 [1] . The FinFETs have the 3D channel shown in Fig. 1 , and it increases on-state current (I on ) per footprint, and suppresses short-channel effects (SCEs) and off-state current (I off ).","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"403 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/IWJT.2019.8802897
T. Beck, B. Roelfs
Motivation The need for shrinking dimensions in the area of advanced packaging is creating new challenges for the reliability for future packages. Metal deposits for a variety of different structures as Cu redistribution layers, μ-Vias, Pillars etc. are becoming thinner or smaller thus effecting on the one hand the area of the interconnect surfaces and on the other hand the thermomechanical strength of the structure. As a result material properties are becoming more and more important as they significantly influence the reliability performance. Content One key element to control the material properties is to understand how impurities in the metal layers and the interface affect the reliability and moreover how to control these impurities. This paper describes exemplary how impurities in the low ppm range influence 1. the mechanical properties and thus the reliability of thin Cu redistribution lines and 2. the interface between Cu and Ti or SnAg solder. We identified the critical impurities, measured their concentration level in the metal and the interface by SIMS and linked it to mechanical properties as ductility and tensile strength. We could show that a thermal budget-as it is usually applied in the manufacture of packages -changes indeed mechanical properties depending on the impurity level. The ductility is mostly affected and reduced by certain critical impurities mainly sulfur. This in turn can lead to cracks in Copper RDL especially for sub 5μm lines during thermal treatment. We could show that modified deposits of high purity do not show this thermomechanical change and withstand the thermal budget without degradation of the mechanical properties while fulfilling all other process requirements. Another defect caused by impurities after thermal budget is the appearance of voids at interfaces. We will demonstrate this effect on two different interfaces • between Ti and Cu RDL and • between Cu and SnAg solder material The appearance of voids is again only detected after thermal budget. Void formation is believed to be due to enrichment of the critical impurities at the interface during recrystallization. We applied SIMS on the different interface areas and could show that void appearance correlate with the existence of Sulfur and other critical elements. Again, high purity deposits do not show these voids after thermal budget offering a viable process alternative. A thorough understanding of electrolyte development is necessary to avoid the incorporation of sulfur, chloride and other incorporations as both elements are key constituents of the additive suites. Development of new electrolytes must not only fulfill process needs as shape, via filling etc. but also take purity into consideration. Summary and Outlook Next generations of packages with smaller and thinner Cu structures are depending on high purity deposits to cope with the reliability requirements. We identified the critical impurities and suggest an acceptable level of impurities
{"title":"The Role of Impurities on the Reliability of Cu Interconnects-a Challenge for Advanced Packaging Solutions","authors":"T. Beck, B. Roelfs","doi":"10.23919/IWJT.2019.8802897","DOIUrl":"https://doi.org/10.23919/IWJT.2019.8802897","url":null,"abstract":"Motivation The need for shrinking dimensions in the area of advanced packaging is creating new challenges for the reliability for future packages. Metal deposits for a variety of different structures as Cu redistribution layers, μ-Vias, Pillars etc. are becoming thinner or smaller thus effecting on the one hand the area of the interconnect surfaces and on the other hand the thermomechanical strength of the structure. As a result material properties are becoming more and more important as they significantly influence the reliability performance. Content One key element to control the material properties is to understand how impurities in the metal layers and the interface affect the reliability and moreover how to control these impurities. This paper describes exemplary how impurities in the low ppm range influence 1. the mechanical properties and thus the reliability of thin Cu redistribution lines and 2. the interface between Cu and Ti or SnAg solder. We identified the critical impurities, measured their concentration level in the metal and the interface by SIMS and linked it to mechanical properties as ductility and tensile strength. We could show that a thermal budget-as it is usually applied in the manufacture of packages -changes indeed mechanical properties depending on the impurity level. The ductility is mostly affected and reduced by certain critical impurities mainly sulfur. This in turn can lead to cracks in Copper RDL especially for sub 5μm lines during thermal treatment. We could show that modified deposits of high purity do not show this thermomechanical change and withstand the thermal budget without degradation of the mechanical properties while fulfilling all other process requirements. Another defect caused by impurities after thermal budget is the appearance of voids at interfaces. We will demonstrate this effect on two different interfaces • between Ti and Cu RDL and • between Cu and SnAg solder material The appearance of voids is again only detected after thermal budget. Void formation is believed to be due to enrichment of the critical impurities at the interface during recrystallization. We applied SIMS on the different interface areas and could show that void appearance correlate with the existence of Sulfur and other critical elements. Again, high purity deposits do not show these voids after thermal budget offering a viable process alternative. A thorough understanding of electrolyte development is necessary to avoid the incorporation of sulfur, chloride and other incorporations as both elements are key constituents of the additive suites. Development of new electrolytes must not only fulfill process needs as shape, via filling etc. but also take purity into consideration. Summary and Outlook Next generations of packages with smaller and thinner Cu structures are depending on high purity deposits to cope with the reliability requirements. We identified the critical impurities and suggest an acceptable level of impurities","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131876355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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