Mechanism of Threshold Voltage Instability in SiC MOSFETs and Impacts on Dynamic Switching

Abstract

The threshold voltage ($V_{\text{TH}}$) instability of silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) are investigated by pulsed bias characterizations. The $V_{\text{TH}}$ instability is observed at a time range from nanoseconds (ns) to seconds. The bias induced $V_{\text{TH}}$ shift caused by is observed within 40 ns. It is also found that a negative gate bias induces a negative $V_{\text{TH}}$ shift while a positive gate bias induces a positive $V_{\text{TH}}$ shift. The carrier trapping and de-trapping processes into the gate oxide cause the $V_{\text{TH}}$ instabilities and they are explained by the energy band diagrams. The TCAD simulations are performed to demonstrate the exsistence of the electric fields to sweep carriers into the trapping region under both positive and negative gate bias conditions. The capacitance-voltage characterizations and first-principles calculations are further carried out to evaluate the defect distribution and explore the intrinsic source of high-density interface traps near the SiC-SiO2 interface.