Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147664
Jiahong Du, Shu-Ting Yang, Guangwei Xu, Shibing Long
In this work, we investigate the surge current ruggedness and role of the conductivity modulation in the vertical GaN-on-GaN PiN diode. With varying $t_{text{surge}}$ (5 µs~10 ms) and [peak Up to 10 kA/cm2, the evolvement of surge current capability of vertical GaN-on-GaN PiN diode has been systematically investigated. Owing to the desirable photon- and thermally-enhanced conductivity modulation in the direct-bandgap GaN, a high surge energy density of $282 J/cm^{2}$ has been realized in the vertical GaN-on-GaN PiN diode, showing great potential of vertical GaN-on-GaN PiN diodes for high power electronic applications.
{"title":"Surge Current Ruggedness in Vertical GaN-on-GaN PiN Diode: Role of Conductivity Modulation","authors":"Jiahong Du, Shu-Ting Yang, Guangwei Xu, Shibing Long","doi":"10.1109/ISPSD57135.2023.10147664","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147664","url":null,"abstract":"In this work, we investigate the surge current ruggedness and role of the conductivity modulation in the vertical GaN-on-GaN PiN diode. With varying $t_{text{surge}}$ (5 µs~10 ms) and [peak Up to 10 kA/cm2, the evolvement of surge current capability of vertical GaN-on-GaN PiN diode has been systematically investigated. Owing to the desirable photon- and thermally-enhanced conductivity modulation in the direct-bandgap GaN, a high surge energy density of $282 J/cm^{2}$ has been realized in the vertical GaN-on-GaN PiN diode, showing great potential of vertical GaN-on-GaN PiN diodes for high power electronic applications.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ispsd57135.2023.10147522
{"title":"Awards of ISPSD 2022: The 34th International Symposium on Power Semiconductor Devices and ICS","authors":"","doi":"10.1109/ispsd57135.2023.10147522","DOIUrl":"https://doi.org/10.1109/ispsd57135.2023.10147522","url":null,"abstract":"","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147438
Sara Kochoska, Jaume Roig Guitart, Lukas Richert, B. Vlachakis
SiC MOSFETs experience a wide variety of electro-thermal phenomena during short-circuit (SC) test. A specific feature that is present in SiC MOSFETs is the high dynamic gate current (iG) which may have an influence on device degradation and failure. In recent SiC MOSFET technologies, the iG waveforms captured during SC testing show previously unexplained peaks. In this paper, the authors investigate the causes of these iG peaks using both experimental data and TCAD simulations, where significant effects of the CGD overcharge are observed. Moreover, an iG comparison between different 1.2 kV device designs are performed with emphasis on best iG sensing practices.
SiC mosfet在短路(SC)测试中会经历各种各样的电热现象。SiC mosfet中存在的一个特定特征是高动态栅极电流(iG)，这可能对器件退化和故障产生影响。在最近的SiC MOSFET技术中，SC测试期间捕获的iG波形显示以前无法解释的峰值。在本文中，作者使用实验数据和TCAD模拟研究了这些iG峰的原因，其中观察到CGD过充电的显着影响。此外，在不同的1.2 kV器件设计之间进行了iG比较，重点是最佳的iG传感实践。
{"title":"Gate Current Peaks Due to CGD Overcharge in SiC MOSFETs Under Short-Circuit Test","authors":"Sara Kochoska, Jaume Roig Guitart, Lukas Richert, B. Vlachakis","doi":"10.1109/ISPSD57135.2023.10147438","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147438","url":null,"abstract":"SiC MOSFETs experience a wide variety of electro-thermal phenomena during short-circuit (SC) test. A specific feature that is present in SiC MOSFETs is the high dynamic gate current (iG) which may have an influence on device degradation and failure. In recent SiC MOSFET technologies, the iG waveforms captured during SC testing show previously unexplained peaks. In this paper, the authors investigate the causes of these iG peaks using both experimental data and TCAD simulations, where significant effects of the CGD overcharge are observed. Moreover, an iG comparison between different 1.2 kV device designs are performed with emphasis on best iG sensing practices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114376136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147460
Caien Sun, Zixu Niu, Shu Yang
In this work, an efficient switching transient analytical model is proposed for P-GaN gate HEMTs, in which the dynamic gate capacitance $C_{mathrm{G}}(V_{text{DS}}, V_{text{GS}})$ characteristics during switching transient has been taken into consideration. Meanwhile, the modeling of external inductance, PCB, driver IC and surface mounting technology (SMT) components in the double-pulse characterization platform are taken into consideration. The proposed dynamic capacitance model is validated by the $C-V$ measurements. Consequently, the switching transient analytical model featuring dynamic gate capacitance characteristics can yield improved accuracy, in comparison with the conventional approach with merely static gate capacitance model.
{"title":"Dynamic Gate Capacitance Model for Switching Transient Analysis in P-GaN Gate HEMTs","authors":"Caien Sun, Zixu Niu, Shu Yang","doi":"10.1109/ISPSD57135.2023.10147460","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147460","url":null,"abstract":"In this work, an efficient switching transient analytical model is proposed for P-GaN gate HEMTs, in which the dynamic gate capacitance $C_{mathrm{G}}(V_{text{DS}}, V_{text{GS}})$ characteristics during switching transient has been taken into consideration. Meanwhile, the modeling of external inductance, PCB, driver IC and surface mounting technology (SMT) components in the double-pulse characterization platform are taken into consideration. The proposed dynamic capacitance model is validated by the $C-V$ measurements. Consequently, the switching transient analytical model featuring dynamic gate capacitance characteristics can yield improved accuracy, in comparison with the conventional approach with merely static gate capacitance model.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147658
Ryan Fang, Yijing Feng, Jessica Chong, Kaiman Chan, U. Radhakrishna, Lan We
GaN HEMTs are actively explored for power elec-tronics (e.g. power converters) due to its superior material properties. High-quality compact model addressing critical behaviors of power GaN devices is in demand for large-scale industry deployment. This paper presents the MVSG model for power GaN devices, which has versatile field plate and gate current configurations. The paper also highlights the modeling strategies for important behaviors such as thermal effects, trapping effects and p-GaN gate stack. Thermal effects are represented through a flexible thermal sub-circuit accounting for both self-heating and external thermal coupling. A comprehensive charge trapping model included in MVSG is able to describe both gate- and drain-lag. The newest addition, the p-GaN module, is also introduced in order to accurately model both static and dynamic behaviors due to the Schottky or hybrid p-GaN gate stacks, which is widely used in power GaN devices to achieve enhancement mode operations. The paper explained the physics-based power MVSG model implementation together with the underlying physics. Examples of model usage demonstrate the effectiveness of this comprehensive power GaN compact model.
{"title":"Comprehensive MVSG Compact Model for Power GaN Devices","authors":"Ryan Fang, Yijing Feng, Jessica Chong, Kaiman Chan, U. Radhakrishna, Lan We","doi":"10.1109/ISPSD57135.2023.10147658","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147658","url":null,"abstract":"GaN HEMTs are actively explored for power elec-tronics (e.g. power converters) due to its superior material properties. High-quality compact model addressing critical behaviors of power GaN devices is in demand for large-scale industry deployment. This paper presents the MVSG model for power GaN devices, which has versatile field plate and gate current configurations. The paper also highlights the modeling strategies for important behaviors such as thermal effects, trapping effects and p-GaN gate stack. Thermal effects are represented through a flexible thermal sub-circuit accounting for both self-heating and external thermal coupling. A comprehensive charge trapping model included in MVSG is able to describe both gate- and drain-lag. The newest addition, the p-GaN module, is also introduced in order to accurately model both static and dynamic behaviors due to the Schottky or hybrid p-GaN gate stacks, which is widely used in power GaN devices to achieve enhancement mode operations. The paper explained the physics-based power MVSG model implementation together with the underlying physics. Examples of model usage demonstrate the effectiveness of this comprehensive power GaN compact model.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129481201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage ($V_{G}$) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under $V_{G}$ overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like $V_{G}$ overshoots with pulse width down to 20 ns and $dV_{G} /dt$ up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency ($f_{text{sw}}$). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of $V_{G}$ overshoot ($V_{mathrm{G}(text{PK})}$) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max $V_{mathrm{G}(text{PK})}$ for 10-year gate lifetime is predicted under different $f_{text{SW}}$ in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT's converter applications and a new method for the device gate qualification.
{"title":"Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching","authors":"Bixuan Wang, Ruizhe Zhang, Hengyu Wang, Quanbo He, Q. Song, Qiang Li, F. Udrea, Yuhao Zhang","doi":"10.1109/ISPSD57135.2023.10147610","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147610","url":null,"abstract":"The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage ($V_{G}$) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under $V_{G}$ overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like $V_{G}$ overshoots with pulse width down to 20 ns and $dV_{G} /dt$ up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency ($f_{text{sw}}$). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of $V_{G}$ overshoot ($V_{mathrm{G}(text{PK})}$) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max $V_{mathrm{G}(text{PK})}$ for 10-year gate lifetime is predicted under different $f_{text{SW}}$ in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT's converter applications and a new method for the device gate qualification.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116508227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ispsd57135.2023.10147733
{"title":"The 36th International Symposium on Power Semiconductor Devices and ICs","authors":"","doi":"10.1109/ispsd57135.2023.10147733","DOIUrl":"https://doi.org/10.1109/ispsd57135.2023.10147733","url":null,"abstract":"","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125969980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147726
T. Ohashi, H. Kono, S. Asaba, Hideki Hayakawa, Takahiro Ogata, R. Iijima
In SBD-embedded SiC MOSFETs, we attempted to improve the surge current capability while suppressing the bipolar operation that causes long-term reliability problems. By incorporating trigger p-n diodes that induce conductivity modulation, we expected that higher current could flow with a low voltage and the surge current capability would be improved. The effectiveness of the trigger diode was confirmed by preliminary TCAD simulation, and SBD-embedded SiC MOSFETs with trigger diodes were fabricated. By placing SBDs in the trigger diode region at the same intervals as in the cell region, maximum current density without bipolar operation was maintained. By distributing 3 to 4 adjacent trigger diodes over the entire chip, the conductivity modulation and heat generation were spread out over the entire chip, and the surge current capability was improved by 1.43 times compared with an SBD-embedded SiC MOSFET without trigger diodes.
{"title":"Improvement of Surge Current Capability in SBD-embedded SiC MOSFETs by Introducing Trigger p-n Diodes","authors":"T. Ohashi, H. Kono, S. Asaba, Hideki Hayakawa, Takahiro Ogata, R. Iijima","doi":"10.1109/ISPSD57135.2023.10147726","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147726","url":null,"abstract":"In SBD-embedded SiC MOSFETs, we attempted to improve the surge current capability while suppressing the bipolar operation that causes long-term reliability problems. By incorporating trigger p-n diodes that induce conductivity modulation, we expected that higher current could flow with a low voltage and the surge current capability would be improved. The effectiveness of the trigger diode was confirmed by preliminary TCAD simulation, and SBD-embedded SiC MOSFETs with trigger diodes were fabricated. By placing SBDs in the trigger diode region at the same intervals as in the cell region, maximum current density without bipolar operation was maintained. By distributing 3 to 4 adjacent trigger diodes over the entire chip, the conductivity modulation and heat generation were spread out over the entire chip, and the surge current capability was improved by 1.43 times compared with an SBD-embedded SiC MOSFET without trigger diodes.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel junction termination technique (JTT) is proposed, which combines three techniques of the optimum variation lateral doping (OPTVLD), buried-layer (BL) and high-k (HK). By utilizing the OPTVLD and BL techniques, an ideal electric field distribution is achieved, resulting in excellent cost-performance. Moreover, by adopting a SrTiO3 film with high permittivity, which induces bound charges that respond automatically to the deviated charges, an extraordinary anti-charge-deviation ability is obtained for the first time. According to the simulation results, in comparison with the conventional JTT structure without the SrTiO3 film, the proposed one gets better process windows increased by 93.3%, 73.9%, 73.9% and 61.3%, with respect to the deviation factors of dose, temperature, heating time and interface charge, respectively. Moreover, since the proposed JTT can be realized by BiCMOS-compatible process, it is budget-friendly and highly feasible.
{"title":"A Novel Junction Termination Technique with Excellent Cost-Performance and Extraordinary Anti-Charge-Deviation Ability","authors":"Junji Cheng, Weisen Meng, B. Yi, Haimeng Huang, Keqiang Ma, Xinkai Guo, Hongqiang Yang, Zhiming Wang, Guoyi Zhang","doi":"10.1109/ISPSD57135.2023.10147685","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147685","url":null,"abstract":"A novel junction termination technique (JTT) is proposed, which combines three techniques of the optimum variation lateral doping (OPTVLD), buried-layer (BL) and high-k (HK). By utilizing the OPTVLD and BL techniques, an ideal electric field distribution is achieved, resulting in excellent cost-performance. Moreover, by adopting a SrTiO3 film with high permittivity, which induces bound charges that respond automatically to the deviated charges, an extraordinary anti-charge-deviation ability is obtained for the first time. According to the simulation results, in comparison with the conventional JTT structure without the SrTiO3 film, the proposed one gets better process windows increased by 93.3%, 73.9%, 73.9% and 61.3%, with respect to the deviation factors of dose, temperature, heating time and interface charge, respectively. Moreover, since the proposed JTT can be realized by BiCMOS-compatible process, it is budget-friendly and highly feasible.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"130 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130150875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147458
Junting Chen, Tao Chen, Zuoheng Jiang, Chengcai Wang, Zheyang Zheng, Jin Wei, K. J. Chen, M. Hua
This work investigates the performance of PFB-HEMTs during switching transients at a circuit level by means of mixed-mode (device/circuit) TCAD simulation. The PFB-HEMTs have been recently proposed to have a higher threshold voltage ($V_{text{TH}}$) comparing to conventional Schottky-type $p$-GaN gate HEMTs, by inserting a normally-on $p$-channel FET between the gate and source of a conventional device. In this simulation, it is found that the on-resistance of the $p$-FET should be adequately low to maintain the high $V_{text{TH}}$ of the PFB-HEMTs during fast switching transients, thus to prevent false turn-on phenomenon. The efficiency of a buck convertor, by replacing the synchronous switch from a conventional device to a PFB-HEMT, increases from 95.2% to 96.7% at 1 MHz.
{"title":"Switching Performance of GaN $p$-FET-bridge (PFB-) HEMTs Studied with Mixed-mode TCAD Simulation","authors":"Junting Chen, Tao Chen, Zuoheng Jiang, Chengcai Wang, Zheyang Zheng, Jin Wei, K. J. Chen, M. Hua","doi":"10.1109/ISPSD57135.2023.10147458","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147458","url":null,"abstract":"This work investigates the performance of PFB-HEMTs during switching transients at a circuit level by means of mixed-mode (device/circuit) TCAD simulation. The PFB-HEMTs have been recently proposed to have a higher threshold voltage ($V_{text{TH}}$) comparing to conventional Schottky-type $p$-GaN gate HEMTs, by inserting a normally-on $p$-channel FET between the gate and source of a conventional device. In this simulation, it is found that the on-resistance of the $p$-FET should be adequately low to maintain the high $V_{text{TH}}$ of the PFB-HEMTs during fast switching transients, thus to prevent false turn-on phenomenon. The efficiency of a buck convertor, by replacing the synchronous switch from a conventional device to a PFB-HEMT, increases from 95.2% to 96.7% at 1 MHz.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130257124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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