Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto
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引用次数: 17
Abstract
We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.
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