Chiplets Integrated Solution with FO-EB Package in HPC and Networking Application

Abstract

Since its introduction in the 1960s, high performance computing (HPC) has made enormous contribution to scientific, engineering and industrial competitiveness as well as other goverment missions. High data rate with high speed transmission has been required for networking and high performance computing application, the chip size and package design has been become larger and larger. Accompanied by the big size design with package, the physical limits has the high cost for the advanced silicon node. The demand for higher functionality devices drives integration technologies to overcome limitations in Moore’s Law. Heterogeneous integration is the one of technologies to meet high performance computing application standards using high bandwidth and Input/Output (I/O) density. The split die of integration in package is the best solution to increase gross die with wafer good yield rate for cost efficiency, and Fan-out Embedded Bridge (FO-EB) Package would be the best representative for HPC and Networking application.The FO-EB is meaning spilt dies with embedded bridge die in fan out package which Inter Connect Die (ICD) become silicon bridge die to do the communications for high electrical performance purpose. Comparing with 2.5D package and FO-MCM package, FO-EB package warpage not only close with 2.5D package, but also better than FO-MCM (Fan-out Multi Chip Module) package. Besides, the electrical performance for high bandwidth memory as good as 2.5D package and FO-MCM package. The FO-EB package has integrated silicon ICD which means provide interconnections between spilt dies with short distance and the package model is more flexable than 2.5D package. That is why FO-EB would be the better choice for HPC and Networking application.The reason we choose FO-EB because it can contribute the same electrical performance to 2.5D package with FO-MCM package and the package warpgae well to be controlled. In this paper, we like to discuss a designed to evaluate the FO-EB and do the measurement comparsion for the warpage, and do the electrical preformance comparsion for the 2.5D, FO-EB and FO-MCM packages. Finally, this paper will find out the chiplets Integrated solution with FO-EB Package in HPC and Networking Application.