Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00332
Krutikesh Sahoo, Uneeb Rathore, Siva Chandra Jangam, Tri Nguyen, D. Markovic, S. Iyer
This work successfully demonstrates functional multi-dielet communication on Silicon Interconnect Fabric (Si-IF) platform using Simple Universal Parallel intERface for CHIPS or SuperCHIPS interface at < 10 μm bump pitch. SuperCHIPS interfaces were implemented in two different functional assemblies for the first time at < 10 μm pitch. The first assembly is used to study the variation in SuperCHIPS link latency and energy/bit with respect to frequency and operating voltage (VDD) scaling. At nominal voltage (VDD) of 0.8V, the measured link data rate is 3 Gbps/link with < 20 ps latency. The second assembly consists of 2×2 dielets on Si-IF, which communicate using multiple SuperCHIPS interfaces mediated by a Streaming Near Range-10pm (SNR-10) channel and protocol. The measured inter-dielet bandwidth of the 2×2 system is 492.8 Gbps.
{"title":"Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric","authors":"Krutikesh Sahoo, Uneeb Rathore, Siva Chandra Jangam, Tri Nguyen, D. Markovic, S. Iyer","doi":"10.1109/ectc51906.2022.00332","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00332","url":null,"abstract":"This work successfully demonstrates functional multi-dielet communication on Silicon Interconnect Fabric (Si-IF) platform using Simple Universal Parallel intERface for CHIPS or SuperCHIPS interface at < 10 μm bump pitch. SuperCHIPS interfaces were implemented in two different functional assemblies for the first time at < 10 μm pitch. The first assembly is used to study the variation in SuperCHIPS link latency and energy/bit with respect to frequency and operating voltage (VDD) scaling. At nominal voltage (VDD) of 0.8V, the measured link data rate is 3 Gbps/link with < 20 ps latency. The second assembly consists of 2×2 dielets on Si-IF, which communicate using multiple SuperCHIPS interfaces mediated by a Streaming Near Range-10pm (SNR-10) channel and protocol. The measured inter-dielet bandwidth of the 2×2 system is 492.8 Gbps.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115630126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00259
Udara S. Somarathna, M. Alhendi, B. Garakani, M. Poliks, D. Weerawarne, J. Iannotti, C. Kapusta, N. Stoffel, S. G. Gonya
Reliability of all-printed vias fabricated on flexible polymer substrates is crucial for the proper functionality of flexible hybrid electronics (FHE) which involve interconnected multilayer electronic circuitry. Existing literature primarily focuses on the mechanical reliability of all-printed vias on flexible polymer substrates fabricated by screen printing and inkjet printing techniques. Therefore, in this work, we present new experimental evidence on the reliability of all-printed vias under thermal shock. The details of the fabrication process, optical characterization, and thermal shock testing are discussed in this paper. Two different fabrication process flows were adopted to obtain all-printed partially-filled blind vias and wall-coated through-hole vias. Vias of 50 - 300 μm diameter were laser drilled on a 3-mil polyimide substrate and printed by screen printing and aerosol-jet printing techniques using three types of microparticle- and nanoparticle-based conductive inks of different viscosities. The performance of the all-printed vias was evaluated based on the interlayer electrical connectivity and the change in electrical resistance after exposure to repeated thermal shock cycles. The experimental results show that the all-printed vias are robust and reliable under thermal shock in the temperature (°C) range of -55 to 125.
{"title":"The Effect of Thermal Stress on the Reliability of all-Printed Vias on Flexible Substrates","authors":"Udara S. Somarathna, M. Alhendi, B. Garakani, M. Poliks, D. Weerawarne, J. Iannotti, C. Kapusta, N. Stoffel, S. G. Gonya","doi":"10.1109/ectc51906.2022.00259","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00259","url":null,"abstract":"Reliability of all-printed vias fabricated on flexible polymer substrates is crucial for the proper functionality of flexible hybrid electronics (FHE) which involve interconnected multilayer electronic circuitry. Existing literature primarily focuses on the mechanical reliability of all-printed vias on flexible polymer substrates fabricated by screen printing and inkjet printing techniques. Therefore, in this work, we present new experimental evidence on the reliability of all-printed vias under thermal shock. The details of the fabrication process, optical characterization, and thermal shock testing are discussed in this paper. Two different fabrication process flows were adopted to obtain all-printed partially-filled blind vias and wall-coated through-hole vias. Vias of 50 - 300 μm diameter were laser drilled on a 3-mil polyimide substrate and printed by screen printing and aerosol-jet printing techniques using three types of microparticle- and nanoparticle-based conductive inks of different viscosities. The performance of the all-printed vias was evaluated based on the interlayer electrical connectivity and the change in electrical resistance after exposure to repeated thermal shock cycles. The experimental results show that the all-printed vias are robust and reliable under thermal shock in the temperature (°C) range of -55 to 125.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116920127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00016
Shoya Sekiguchi, K. Oki, Shoko Mishima, Yuya Fukata, Kaho Shibasaki, N. Ishikawa, T. Ogata
Fifth generation (5G) and beyond wireless networks require high-frequency signals for high-speed, high-capacity, and low-latency communication. These high-frequency signals undergo extensive transmission losses. Furthermore, the terahertz band is being considered for 6th-generation (6G) networks. Therefore, transmission loss must be considered in the design of antenna components and high-frequency circuit boards. To reduce the transmission loss, we developed a material with alow dielectric constant (Dk) and low dissipation factor (Df). We used polyphenylene ether (PPE) owing to its low Dk and Df. We modified the structure of PPE to obtain soluble PPE that dissolves in common organic solvents. The composite material was prepared using the as-prepared soluble PPE. The as-prepared soluble-PPE-based composite material (SPCM) exhibited excellent Dk and Df of 3.1 and 0.0013, respectively, at 10 GHz. We fabricated a microstrip line on the SPCM and measured its transmission losses. At 95 GHz, the transmission loss was 14.2 dB/100 mm. This result can be attributed to the excellent dielectric properties and small surface roughness offered by the excellent hydrophobicity of the SPCM.
{"title":"Evaluation of the Transmission Loss of Soluble Polyphenylene Ether Composite Material in a Millimeter-Wave Region","authors":"Shoya Sekiguchi, K. Oki, Shoko Mishima, Yuya Fukata, Kaho Shibasaki, N. Ishikawa, T. Ogata","doi":"10.1109/ectc51906.2022.00016","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00016","url":null,"abstract":"Fifth generation (5G) and beyond wireless networks require high-frequency signals for high-speed, high-capacity, and low-latency communication. These high-frequency signals undergo extensive transmission losses. Furthermore, the terahertz band is being considered for 6th-generation (6G) networks. Therefore, transmission loss must be considered in the design of antenna components and high-frequency circuit boards. To reduce the transmission loss, we developed a material with alow dielectric constant (Dk) and low dissipation factor (Df). We used polyphenylene ether (PPE) owing to its low Dk and Df. We modified the structure of PPE to obtain soluble PPE that dissolves in common organic solvents. The composite material was prepared using the as-prepared soluble PPE. The as-prepared soluble-PPE-based composite material (SPCM) exhibited excellent Dk and Df of 3.1 and 0.0013, respectively, at 10 GHz. We fabricated a microstrip line on the SPCM and measured its transmission losses. At 95 GHz, the transmission loss was 14.2 dB/100 mm. This result can be attributed to the excellent dielectric properties and small surface roughness offered by the excellent hydrophobicity of the SPCM.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117352587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00243
B. Garakani, K. U. S. Somarathna, Riadh Al-haidari, Firas W Alshatnavi, D. Smilgies, M. Poliks
In this study, commercially available stretchable hybrid conductors including silver flakes in an elastomeric matrix were screen printed on thermoplastic polyurethane (TPU) followed by encapsulation via the stretchable dielectric. Test vehicles include straight and serpentine lines with various thicknesses and wavelengths, respectively. Metrology was also performed to assess line thickness, width, and variability. The modular force stage (MFS) was used to characterize the initiation and propagation of microcracks. The results of the uniaxial tensile test showed that increasing the strain amplitude resulted in an increase in the electrical resistance and the rate of damage accumulation in the serpentine traces was lower than that of the straight traces. Additionally, the serpentine trace with the highest ratio of meander arm length to curvature remained conductive up to a strain amplitude of 150%. A systematic increase in electrical resistance from cycle to cycle was observed when the conductor was subjected to a strain amplitude of 10% for 1000 stretching cycles. The effect of processing conditions as well as test conditions will be discussed in detail.
{"title":"Fabrication, Characterization, and Electromechanical Reliability of Stretchable Circuitry for Health Monitoring Systems","authors":"B. Garakani, K. U. S. Somarathna, Riadh Al-haidari, Firas W Alshatnavi, D. Smilgies, M. Poliks","doi":"10.1109/ectc51906.2022.00243","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00243","url":null,"abstract":"In this study, commercially available stretchable hybrid conductors including silver flakes in an elastomeric matrix were screen printed on thermoplastic polyurethane (TPU) followed by encapsulation via the stretchable dielectric. Test vehicles include straight and serpentine lines with various thicknesses and wavelengths, respectively. Metrology was also performed to assess line thickness, width, and variability. The modular force stage (MFS) was used to characterize the initiation and propagation of microcracks. The results of the uniaxial tensile test showed that increasing the strain amplitude resulted in an increase in the electrical resistance and the rate of damage accumulation in the serpentine traces was lower than that of the straight traces. Additionally, the serpentine trace with the highest ratio of meander arm length to curvature remained conductive up to a strain amplitude of 150%. A systematic increase in electrical resistance from cycle to cycle was observed when the conductor was subjected to a strain amplitude of 10% for 1000 stretching cycles. The effect of processing conditions as well as test conditions will be discussed in detail.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00350
Heeseok Lee, Kyojin Hwang, Henry H. Kwon, Jisoo Hwang, Junso Pak, Ju Yeon Choi
Through this work, two-sided model (TSM) for embedded discrete capacitor is presented by authors. When two sides of the discrete ceramic capacitor embedded in multi-layered organic substrate or redistribution layer (RDL) based fan-out package are connected to metal layers in substrate or RDL, which are placed over and under the embedded capacitor, the proposed TSM of capacitor is required to properly represent the impedance characteristic of power delivery network (PDN). It is demonstrated that impedance representing PDN with one-sided model is not proper and accurate, based on which it will be addressed that power delivery network (PDN) should be properly represented and optimized by using TSM of embedded capacitor.
{"title":"Modeling High-Frequency and DC Path of Embedded Discrete Capacitor Connected by Double-Side Terminals with Multi-layered Organic Substrate and RDL-based Fan-out Package","authors":"Heeseok Lee, Kyojin Hwang, Henry H. Kwon, Jisoo Hwang, Junso Pak, Ju Yeon Choi","doi":"10.1109/ectc51906.2022.00350","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00350","url":null,"abstract":"Through this work, two-sided model (TSM) for embedded discrete capacitor is presented by authors. When two sides of the discrete ceramic capacitor embedded in multi-layered organic substrate or redistribution layer (RDL) based fan-out package are connected to metal layers in substrate or RDL, which are placed over and under the embedded capacitor, the proposed TSM of capacitor is required to properly represent the impedance characteristic of power delivery network (PDN). It is demonstrated that impedance representing PDN with one-sided model is not proper and accurate, based on which it will be addressed that power delivery network (PDN) should be properly represented and optimized by using TSM of embedded capacitor.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127499316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00121
S. Saxena, C. Hess, M. Quarantelli, Alberto Piadena, L. Weiland, R. Vallishayee, Yuan Yu, D. Ciplickas, T. Brożek, A. Strojwas
Advanced IC’s built with recent technology nodes take advantage of the process induced mechanical stress, which is used as one of the transistor performance boosters. Modulation of the stress level, experienced by silicon chip, has significant impact on its performance and reliability. Therefore, monitoring of this stress through wafer manufacturing and packaging process is of high importance. We have developed an in-die-embedded stress sensor, testable with standard product test that can with help measuring and monitoring stress level in the die. The sensor design was demonstrated for multiple advanced FinFET technology nodes (< 14nm). We have confirmed high sensitivity across process corners and temperature with consistent results between electrical wafer sort (EWS) and final test (FT). The results from the mechanical stress sensors indicate that the stress non-uniformity across the wafer is preserved through wafer dicing/thinning/packaging process. Statistical analysis of the sensor results enables detection of wafer patterns and outlier identification at EWS and subsequent FT after assembly enables detection of abnormal mechanical stress changes due to packaging. This mechanical stress sensor provides differentiated data for EWS, FT, and Burn-In (BI) to create product relevant screening specs for improved product reliability and can provide an early alarm for the product reliability risk due to effects such as delamination or cracks. This sensor has been implemented in the PDF Solutions’ CV Core® system which enables for in-field tracking and analyzing the sensor signals to detect and mitigate the potentially disastrous reliability failures.
{"title":"Tracking in-die mechanical stress through silicon embedded sensors for advanced packaging applications","authors":"S. Saxena, C. Hess, M. Quarantelli, Alberto Piadena, L. Weiland, R. Vallishayee, Yuan Yu, D. Ciplickas, T. Brożek, A. Strojwas","doi":"10.1109/ectc51906.2022.00121","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00121","url":null,"abstract":"Advanced IC’s built with recent technology nodes take advantage of the process induced mechanical stress, which is used as one of the transistor performance boosters. Modulation of the stress level, experienced by silicon chip, has significant impact on its performance and reliability. Therefore, monitoring of this stress through wafer manufacturing and packaging process is of high importance. We have developed an in-die-embedded stress sensor, testable with standard product test that can with help measuring and monitoring stress level in the die. The sensor design was demonstrated for multiple advanced FinFET technology nodes (< 14nm). We have confirmed high sensitivity across process corners and temperature with consistent results between electrical wafer sort (EWS) and final test (FT). The results from the mechanical stress sensors indicate that the stress non-uniformity across the wafer is preserved through wafer dicing/thinning/packaging process. Statistical analysis of the sensor results enables detection of wafer patterns and outlier identification at EWS and subsequent FT after assembly enables detection of abnormal mechanical stress changes due to packaging. This mechanical stress sensor provides differentiated data for EWS, FT, and Burn-In (BI) to create product relevant screening specs for improved product reliability and can provide an early alarm for the product reliability risk due to effects such as delamination or cracks. This sensor has been implemented in the PDF Solutions’ CV Core® system which enables for in-field tracking and analyzing the sensor signals to detect and mitigate the potentially disastrous reliability failures.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126039353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00011
Mike Tsai, Wynn Li, Ethan Ding, Tim Chang, Kevin Chang, Karina Chang, Eric He, J. Chen, Rios Hsieh, Ryan Chiu, James Lin
The wearable devices demand small form factor and drive more function such as heartbeat detection, electrocardiogram detection functions, and sensors. Wearable device has become a small medical data center. Therefore, the design trend of wearable products requires smaller module size, multi-IC and component integration, low power consumption and better heat dissipation performance. The module size of the original Single Side SiP (System in Package) products cannot meet the next generation product, and Double Side SiP structure is expected to provide solutions for more diverse applications of wearable products in the future. The Double Side SiP structure can provide higher integration and performance. Package can be reduced to about 40~60% lighter and thinner to improve power supply efficiency and to reduce noise emission. This paper will demonstrate Double Side SiP of PKG structure with strip grinding process to check PKG die strength as a function of thickness. By using simulation and experiment, the ELK stress performance with 3-point test methodology is studied to select the suitable Double Side SiP structure for end product of board level manufacturing process. From electrical integration point of view, the shorter signal transmission path is required to get good electrical performance (SI: Signal Integrity & PI: Power Integrity) than a side by side flip chip base structure. The Double Side SiP module can provide an advanced solution to address the module size, cost, performance, and time-to-market requirement for 5G and wearable products in near future.The performance verification will be confirmed by simulation and measurement. The reliability testing verification includes the TCT, HTSL and u-HAST (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results of the Double Side SiP structure. Finally, this paper summarizes Double Side SiP structure and feasibility data for future 5G and wearable devices application.
可穿戴设备需要小尺寸的外形，并驱动更多的功能，如心跳检测、心电图检测功能和传感器。可穿戴设备已经成为小型医疗数据中心。因此，可穿戴产品的设计趋势要求更小的模块尺寸，多ic和组件集成，低功耗和更好的散热性能。原有单端SiP (System in Package)产品的模块尺寸无法满足下一代产品的需求，双端SiP结构有望为未来可穿戴产品更多样化的应用提供解决方案。双面SiP结构可以提供更高的集成度和性能。封装可以减少到约40~60%的重量和厚度，以提高供电效率和降低噪音排放。本文将演示带磨削PKG结构的双面SiP，以校核PKG模具强度随厚度的函数。采用仿真和实验相结合的方法，采用三点测试法对ELK应力性能进行了研究，为板级制造工艺的最终产品选择合适的双面SiP结构。从电气集成的角度来看，与并排倒装芯片基础结构相比，需要更短的信号传输路径来获得良好的电气性能(SI:信号完整性和PI:功率完整性)。双面SiP模块可以为解决未来5G和可穿戴产品在模块尺寸、成本、性能和上市时间等方面的需求提供先进的解决方案。性能验证将通过仿真和测量进行验证。可靠性测试验证包括双侧SiP结构的TCT、HTSL和u-HAST(温度循环测试、高温储存测试、无偏置HAST)结果。最后总结了双面SiP的结构和未来5G及可穿戴设备应用的可行性数据。
{"title":"Double Side SiP of Structure Strength Analysis for 5G and Wearable Application","authors":"Mike Tsai, Wynn Li, Ethan Ding, Tim Chang, Kevin Chang, Karina Chang, Eric He, J. Chen, Rios Hsieh, Ryan Chiu, James Lin","doi":"10.1109/ectc51906.2022.00011","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00011","url":null,"abstract":"The wearable devices demand small form factor and drive more function such as heartbeat detection, electrocardiogram detection functions, and sensors. Wearable device has become a small medical data center. Therefore, the design trend of wearable products requires smaller module size, multi-IC and component integration, low power consumption and better heat dissipation performance. The module size of the original Single Side SiP (System in Package) products cannot meet the next generation product, and Double Side SiP structure is expected to provide solutions for more diverse applications of wearable products in the future. The Double Side SiP structure can provide higher integration and performance. Package can be reduced to about 40~60% lighter and thinner to improve power supply efficiency and to reduce noise emission. This paper will demonstrate Double Side SiP of PKG structure with strip grinding process to check PKG die strength as a function of thickness. By using simulation and experiment, the ELK stress performance with 3-point test methodology is studied to select the suitable Double Side SiP structure for end product of board level manufacturing process. From electrical integration point of view, the shorter signal transmission path is required to get good electrical performance (SI: Signal Integrity & PI: Power Integrity) than a side by side flip chip base structure. The Double Side SiP module can provide an advanced solution to address the module size, cost, performance, and time-to-market requirement for 5G and wearable products in near future.The performance verification will be confirmed by simulation and measurement. The reliability testing verification includes the TCT, HTSL and u-HAST (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results of the Double Side SiP structure. Finally, this paper summarizes Double Side SiP structure and feasibility data for future 5G and wearable devices application.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126164130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00091
S. J. Gräfner, J. H. Huang, Y. A. Chen, P. S. Shih, C. H. Huang, C. Kao
The electroless plating process is probably one of the most promising methods to overcome the barriers of the solder technology in scaling-down fine-pitch interconnection in the chip packaging industry. To optimize this process, we propose the usage of numerical simulation as a key step towards mass production. This study develops two fundamental simulation models for a rectangular and diamond pattern of pillars, respectively. For both arrangements, the pressure drop and further flow characteristics are investigated dependent on the following parameters: pillar diameter D, pitch-to-diameter ratio S/D and height-to-diameter ratio H/D and superficial velocity U. The results show that a lower pressure drop can be achieved for higher values of these three geometrical parameters. The flow in a rectangular pattern is more likely to form vortices between the wake and front region of the pillars and to form a focused stream between the side areas of the pillars for high D, low S/D, high H/D and high U. The diamond array is less likely for vortex generation and favors to form an S-shaped stream through the arrangement of pillars. However, the pressure drop of the diamond pattern tends to be considerably higher compared to the rectangular counterpart for large D, high S/D and high H/D due to enhanced stagnation forces. Moreover, the developed numerical models show a good match with experimental data from the literature.
{"title":"Key steps from laboratory towards mass production: Optimization of electroless plating process through numerical simulation","authors":"S. J. Gräfner, J. H. Huang, Y. A. Chen, P. S. Shih, C. H. Huang, C. Kao","doi":"10.1109/ectc51906.2022.00091","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00091","url":null,"abstract":"The electroless plating process is probably one of the most promising methods to overcome the barriers of the solder technology in scaling-down fine-pitch interconnection in the chip packaging industry. To optimize this process, we propose the usage of numerical simulation as a key step towards mass production. This study develops two fundamental simulation models for a rectangular and diamond pattern of pillars, respectively. For both arrangements, the pressure drop and further flow characteristics are investigated dependent on the following parameters: pillar diameter D, pitch-to-diameter ratio S/D and height-to-diameter ratio H/D and superficial velocity U. The results show that a lower pressure drop can be achieved for higher values of these three geometrical parameters. The flow in a rectangular pattern is more likely to form vortices between the wake and front region of the pillars and to form a focused stream between the side areas of the pillars for high D, low S/D, high H/D and high U. The diamond array is less likely for vortex generation and favors to form an S-shaped stream through the arrangement of pillars. However, the pressure drop of the diamond pattern tends to be considerably higher compared to the rectangular counterpart for large D, high S/D and high H/D due to enhanced stagnation forces. Moreover, the developed numerical models show a good match with experimental data from the literature.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00260
Mohammad Al Ahsan, S. Hasan, M. A. Haq, J. Suhling, P. Lall
Solder joints in electronic assemblies are frequently exposed to thermal cycling environments in their service life or during accelerated life testing where temperature variations occur from very low to high temperature. Due to the CTE mismatches of the assembly materials, cyclic temperature leads to damage accumulation due to shear fatigue in the solder joints. In addition, dwell periods at the high temperature extremes will cause thermal aging phenomena and additional microstructural evolution and material property degradation. Further aging effects can occur during the ramp periods between the low and high temperature extremes.While changes in solder materials during aging have been examined in detail in prior studies, there have been limited studies examining material evolution occurring during other thermal exposures such as thermal cycling and thermal shock. In our recent papers, the mechanical behavior evolutions occurring in SAC305 and SAC+3%Bi (SAC_Q) lead free solders have been characterized for up to 20 days of exposure to four different thermal profiles including isothermal aging, slow thermal cycling, thermal shock, and thermal ramping. The degradations in the mechanical properties (modulus, UTS, yield strength) were observed for both miniature bulk samples and solder joints, and then the results were compared for the different exposure profiles. For both bulk samples and joints, the largest changes were observed for the slow thermal cycling profile. In addition, the changes in the SAC+3%Bi solder samples were much smaller than those experienced in the SAC305 solder samples for all of the considered thermal profiles.In the current investigation, we have extended our prior study to examine several different SAC+Bi solder alloys with various bismuth contents. In particular, a family of SAC+Bi alloys with 1%, 2%, and 3% Bi were studied with four different thermal exposure profiles (isothermal aging, slow thermal cycling, thermal shock, and thermal ramping). The primary objective of this study was to determine how much bismuth is needed in the lead-free alloy to mitigate microstructure and material property evolutions during thermal exposures. Use of lower Bi content can lower solder cost and also increase reliability in high strain rate loadings such as shock/drop/vibration.Uniaxial miniature bulk specimens were prepared for the three SAC+Bi alloys using a controlled reflow profile. After fabrication, the samples were then preconditioned by thermal exposure under stress-free conditions for various durations up to 100 days. Several thermal exposure profiles from -40 C to 125 C were examined including: (1) isothermal aging at the high temperature extreme (aging), (2) 150 minute cycles with 45 minutes ramps and 30 minutes dwells (slow thermal cycling), (3) air-to-air thermal shock exposures with 30 minutes dwells and near instantaneous ramps (thermal shock), and (4) 90 minute cycles with 45 minutes ramps and 0 minutes dwells (thermal rampi
{"title":"Mechanical Property Evolution in SAC+Bi Lead-Free Solders Subjected to Various Thermal Exposure Profiles","authors":"Mohammad Al Ahsan, S. Hasan, M. A. Haq, J. Suhling, P. Lall","doi":"10.1109/ectc51906.2022.00260","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00260","url":null,"abstract":"Solder joints in electronic assemblies are frequently exposed to thermal cycling environments in their service life or during accelerated life testing where temperature variations occur from very low to high temperature. Due to the CTE mismatches of the assembly materials, cyclic temperature leads to damage accumulation due to shear fatigue in the solder joints. In addition, dwell periods at the high temperature extremes will cause thermal aging phenomena and additional microstructural evolution and material property degradation. Further aging effects can occur during the ramp periods between the low and high temperature extremes.While changes in solder materials during aging have been examined in detail in prior studies, there have been limited studies examining material evolution occurring during other thermal exposures such as thermal cycling and thermal shock. In our recent papers, the mechanical behavior evolutions occurring in SAC305 and SAC+3%Bi (SAC_Q) lead free solders have been characterized for up to 20 days of exposure to four different thermal profiles including isothermal aging, slow thermal cycling, thermal shock, and thermal ramping. The degradations in the mechanical properties (modulus, UTS, yield strength) were observed for both miniature bulk samples and solder joints, and then the results were compared for the different exposure profiles. For both bulk samples and joints, the largest changes were observed for the slow thermal cycling profile. In addition, the changes in the SAC+3%Bi solder samples were much smaller than those experienced in the SAC305 solder samples for all of the considered thermal profiles.In the current investigation, we have extended our prior study to examine several different SAC+Bi solder alloys with various bismuth contents. In particular, a family of SAC+Bi alloys with 1%, 2%, and 3% Bi were studied with four different thermal exposure profiles (isothermal aging, slow thermal cycling, thermal shock, and thermal ramping). The primary objective of this study was to determine how much bismuth is needed in the lead-free alloy to mitigate microstructure and material property evolutions during thermal exposures. Use of lower Bi content can lower solder cost and also increase reliability in high strain rate loadings such as shock/drop/vibration.Uniaxial miniature bulk specimens were prepared for the three SAC+Bi alloys using a controlled reflow profile. After fabrication, the samples were then preconditioned by thermal exposure under stress-free conditions for various durations up to 100 days. Several thermal exposure profiles from -40 C to 125 C were examined including: (1) isothermal aging at the high temperature extreme (aging), (2) 150 minute cycles with 45 minutes ramps and 30 minutes dwells (slow thermal cycling), (3) air-to-air thermal shock exposures with 30 minutes dwells and near instantaneous ramps (thermal shock), and (4) 90 minute cycles with 45 minutes ramps and 0 minutes dwells (thermal rampi","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125329820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.1109/ectc51906.2022.00224
Romaric Kabre, D. Danovitch, V. Oberson, Magali Cote
A novel approach to achieving low temperature electrically conductive adhesive (ECA) flip chip interconnections of CZT device is proposed. This approach exploits CZT transparency to certain IR radiation wavelengths and the non-thermal effects imparted upon epoxies by such IR radiation. We determine appropriate conditions, such as wavelength, source temperature and exposure time of an IR radiation source. A series of experiments examine the extent of CZT transparency, including the impact of the CZT contact pads. These results are used to determine appropriate cure schedules for selected ECA candidates as characterized by degree of polymerization and volume resistivity. The detailed results presented in this paper demonstrate the ability to maintain CZT temperature significantly lower (by as much as 50°C) than the ECA cure temperature. Further, non-thermal effects, previously documented for IR curing of non-conductive epoxies, are demonstrated for ECA materials, thereby providing important reductions in ECA cure times (as compared to convection curing) while ensuring a high degree of polymerization (>95%) and low volume resistivity (< 5 mΩ.cm). In fact, improved volume resistivity was observed at low temperatures as compared to convection curing; a hypothesis for this improvement is postulated and preliminary validation experiments discussed.
{"title":"Infrared Curing of Flip Chip Electrically Conductive Adhesive (ECA) Interconnections","authors":"Romaric Kabre, D. Danovitch, V. Oberson, Magali Cote","doi":"10.1109/ectc51906.2022.00224","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00224","url":null,"abstract":"A novel approach to achieving low temperature electrically conductive adhesive (ECA) flip chip interconnections of CZT device is proposed. This approach exploits CZT transparency to certain IR radiation wavelengths and the non-thermal effects imparted upon epoxies by such IR radiation. We determine appropriate conditions, such as wavelength, source temperature and exposure time of an IR radiation source. A series of experiments examine the extent of CZT transparency, including the impact of the CZT contact pads. These results are used to determine appropriate cure schedules for selected ECA candidates as characterized by degree of polymerization and volume resistivity. The detailed results presented in this paper demonstrate the ability to maintain CZT temperature significantly lower (by as much as 50°C) than the ECA cure temperature. Further, non-thermal effects, previously documented for IR curing of non-conductive epoxies, are demonstrated for ECA materials, thereby providing important reductions in ECA cure times (as compared to convection curing) while ensuring a high degree of polymerization (>95%) and low volume resistivity (< 5 mΩ.cm). In fact, improved volume resistivity was observed at low temperatures as compared to convection curing; a hypothesis for this improvement is postulated and preliminary validation experiments discussed.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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