Characterization, modeling and optimization of high power module packaging

M. Trivedi, K. Shenai
{"title":"Characterization, modeling and optimization of high power module packaging","authors":"M. Trivedi, K. Shenai","doi":"10.1109/EPEP.1997.634049","DOIUrl":null,"url":null,"abstract":"This paper reports the use of two-dimensional numerical simulations in modeling the effects of packaging on the electrical performance of high-power modules. Non-isothermal simulations are performed to study the performance and failure of IGBTs under short-circuit and clamped inductive switching stress.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"404 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1997.634049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

This paper reports the use of two-dimensional numerical simulations in modeling the effects of packaging on the electrical performance of high-power modules. Non-isothermal simulations are performed to study the performance and failure of IGBTs under short-circuit and clamped inductive switching stress.
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大功率模块封装的特性、建模和优化
本文报道了采用二维数值模拟方法模拟封装对大功率模块电性能的影响。通过非等温模拟研究了igbt在短路和钳位电感开关应力下的性能和失效情况。
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