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Electrical Performance of Electronic Packaging最新文献

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Low-cost technique for reducing the simultaneous switching noise in sub-board packaging configurations 降低分板封装配置中同时开关噪声的低成本技术
Pub Date : 1998-11-01 DOI: 10.1109/96.730428
S. Koike, K. Kaizu
A low-cost technique for reducing simultaneous switching noise in a sub-board packaging configuration has been developed. By using a thin insulator film made of conventional FR4 substrate material, the noise is reduced about 50% when 32 switching gates are simultaneously driven at 622.08 Mb/s in a sub-board with an area of 11/spl times/10 cm.
开发了一种低成本的降低分板封装配置中同时开关噪声的技术。采用传统FR4衬底材料制成的薄绝缘体薄膜,在面积为11/spl × / 10cm的子板上以622.08 Mb/s的速度同时驱动32个开关门时,噪声降低约50%。
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引用次数: 1
Time domain multiconductor transmission line analysis using effective internal impedance 时域多导体传输线有效内阻抗分析
Pub Date : 1997-12-01 DOI: 10.1109/EPEP.1997.634083
Sangwoo Kim, D. Neikirk
A compact skin effect circuit model is used to formulate a time domain boundary condition for lossy transmission lines. The resulting lossless-like multiconductor equations can be used in various time domain calculations, including FDTD.
利用紧凑的趋肤效应电路模型,给出了有耗传输线的时域边界条件。所得的类无损多导体方程可用于各种时域计算,包括时域有限差分法。
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引用次数: 9
Circuit modeling of isolation in flip-chip microwave integrated circuits 倒装微波集成电路的隔离电路建模
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634074
R. Ito, R. Jackson
A circuit model for multi-port flipped-chip packaging of microwave integrated circuits is described. The model topology includes the effect of non-ideal isolation between IC ports and predicts resonance behavior in the millimeterwave range. Measurements of a scale model four port are used for verification.
介绍了微波集成电路中多端口倒装芯片封装的电路模型。模型拓扑包括IC端口之间非理想隔离的影响,并预测毫米波范围内的谐振行为。采用四端口比例模型的测量结果进行验证。
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引用次数: 0
Packaging and power distribution design considerations for a Sun Microsystems desktop workstation Sun Microsystems桌面工作站的封装和配电设计考虑
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634028
L. Smith
The power distribution system will become an increasingly important package design consideration for computer systems such as the Sun Microsystems desktop workstation, at least as important as simultaneous switch. Power distribution impedance is controlled by the switching power supply, bulk capacitance, ceramic capacitance and power plane properties at various portions of the frequency spectrum. A major concern with package power is resonance between chip capacitance and package inductance. The key parameters for package power are the core power supply loop inductance and the inductance and resistance used to connect any decoupling capacitors on the package. Decoupling capacitors on the package can be used but they will not be effective unless the connections to them are specially designed using aggressive technologies.
配电系统将成为诸如Sun Microsystems桌面工作站等计算机系统日益重要的封装设计考虑因素,至少与同步开关同等重要。功率分配阻抗由开关电源、体电容、陶瓷电容和功率平面在频谱各部分的特性控制。封装功率的一个主要问题是芯片电容和封装电感之间的共振。封装功率的关键参数是核心电源回路电感和用于连接封装上任何去耦电容器的电感和电阻。封装上的去耦电容器可以使用,但除非与它们的连接是使用先进技术专门设计的,否则它们不会有效。
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引用次数: 30
Suppression of leakage and crosstalk in typical millimeter-wave flip-chip packages 典型毫米波倒装封装中泄漏和串扰的抑制
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634069
G. Lee, Hai-Young Lee
Leakage phenomena of flip-chip structures on common GaAs and alumina main substrates are characterized using the spectral domain approach to reduce the possible chip-to-chip crosstalk and transmission resonance. We have found that the longitudinal section magnetic mode is dominant for the coplanar waveguide leakage and the leakage can be suppressed by properly managing the gap height and the main substrate thickness in addition to the dielectric constant.
为了减少芯片间串扰和传输共振的可能性,采用谱域方法对普通砷化镓和氧化铝基板上倒装芯片结构的泄漏现象进行了表征。我们发现纵截面磁模是共面波导泄漏的主导模式,通过适当控制缝隙高度和主衬底厚度以及介电常数可以抑制泄漏。
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引用次数: 1
The PSTD algorithm: a fast and accurate time-domain method for electronic package characterization PSTD算法:一种快速、准确的电子封装表征时域方法
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634059
Q. Liu, Y. Li, J. Liao
Conventional finite-difference time-domain (FDTD) methods are very inefficient for simulations of electromagnetic wave propagation in large-scale complex media. This is mainly because of the low-accuracy associated with the spatial discretization in the FDTD methods. As a result, even for a moderate size problem, a large number of cells (typically 10-20 cells per wavelength) are required to obtain reasonably accurate results. This requirement becomes much more stringent for large-scale problems since the dispersion error grows rapidly with the propagation distance. Recently a pseudospectral time-domain (PSTD) algorithm has been developed which requires only two cells per wavelength regardless of the problem size. In terms of spatial discretization, this method is an optimal time-domain solution since it has an infinite order of accuracy in the spatial representation. For a problem with structures much smaller than the smallest wavelength, the PSTD algorithm still provides high accuracy up to a much higher spatial frequency than FDTD methods. In addition, the only error introduced in the PSTD algorithm is the temporal discretization. Unlike the dispersion error in FDTD methods, this error is isotropic and does not increase with the scale of the problem. In this work, we apply the PSTD method to characterize the electrical performance of electronic packages. In particular, it is used to investigate the effects of enclosure resonance and electromagnetic interference.
传统的时域有限差分(FDTD)方法在模拟大规模复杂介质中的电磁波传播时效率很低。这主要是由于时域有限差分法中空间离散化的精度较低。因此,即使对于中等大小的问题,也需要大量的细胞(通常每个波长10-20个细胞)才能获得相当准确的结果。对于大规模问题,由于色散误差随着传播距离的增加而迅速增大,这一要求变得更加严格。近年来,人们提出了一种伪谱时域(PSTD)算法,无论问题大小如何,每个波长只需要两个单元。在空间离散化方面,该方法是一种最优的时域解,因为它在空间表示上具有无限阶的精度。对于比最小波长小得多的结构问题,PSTD算法仍然具有比FDTD方法高得多的空间频率精度。此外,PSTD算法中引入的唯一误差是时间离散化。与FDTD方法中的色散误差不同,该误差是各向同性的,并且不随问题的规模而增加。在这项工作中,我们应用PSTD方法来表征电子封装的电气性能。特别地,它被用来研究外壳共振和电磁干扰的影响。
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引用次数: 1
Characterization of peripheral and core SSOs in a flip-chip package 倒装封装中外设和核心sso的特性
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634053
R. Kollipara, L. Lin, G. Oehrle
Electrical characterization of various SSO (simultaneous switching output) buffers placed on the periphery and in the core of a flip-chip is performed. The multilayer CBGA package has multiple power and ground planes and signal routing layers. Methodology guide lines are developed based on the characterization results.
对放置在倒装芯片外围和核心的各种SSO(同步开关输出)缓冲器进行了电气特性分析。多层CBGA封装具有多个电源层、接地层和信号路由层。方法学指导方针是根据表征结果制定的。
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引用次数: 0
Wideband crosstalk analysis of coupled bondwires buried in high-speed plastic packages 埋在高速塑料封装中的耦合键合线的宽带串扰分析
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634046
Sang-Ki Yun, Hai-Young Lee
Crosstalk of picosecond pulses in bondwires for plastic packaging is analyzed using the full-wave method of moments (MoM) and the FFT algorithm, showing that the static crosstalk model of SPICE is inappropriate for the high-speed package design. Plastic packaging materials significantly increase bondwire crosstalk due to the mutual electromagnetic coupling enhanced by the dielectric and radiation effects.
利用全波矩量法(MoM)和FFT算法分析了塑料封装用键合导线中皮秒脉冲的串扰,表明SPICE的静态串扰模型不适合高速封装设计。由于介质和辐射效应增强了相互电磁耦合,塑料封装材料显著增加了键合线串扰。
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引用次数: 3
Reduction of high-speed signal distortions in double-layered dielectric PCB interconnects 双层介质PCB互连中高速信号失真的降低
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634040
T. Gazizov, N. Leontiev
Characteristics of single and coupled suspended and inverted microstrip lines are calculated by variational method. Experimental waveforms for usual and suspended microstrip are compared. The possibilities of reduction of high-speed signal distortions in PCBs with such lines are shown.
用变分法计算了单微带线和耦合微带线和倒挂微带线的特性。比较了普通微带和悬浮微带的实验波形。显示了用这种线路减少pcb中高速信号失真的可能性。
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引用次数: 10
The enhancement of static simulator package characterization through conductor segmentation 通过导体分割增强静态模拟器封装特性
Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634043
G. Klemens, V. Aparin, K. Gard
A technique is presented for increasing the accuracy of package models produced by static simulation through segmentation of conductors. The lumped circuit elements are better distributed along the leads than when whole conductors are used.
提出了一种通过分割导体来提高静态仿真生成的封装模型精度的方法。集总电路元件沿着引线分布比使用整个导体时更好。
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引用次数: 5
期刊
Electrical Performance of Electronic Packaging
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