Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

Abstract

This paper describes a methodology of creating a built-in test system of a system on chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. The highly compressed test vectors are transferred from the memory to the chosen cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test through test access mechanism (TAM) and standard wrappers. After having tested the first cores under test the TAM of the SoC is partially reconfigured with the help of the partial reconfiguration bitstreams and the till now untested cores are tested by those cores that start to serve as embedded testers. By this traveling reconfiguration and testing the whole circuit can be tested. For test data compression we use a test pattern compaction and compression algorithm called COMPAS. It reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. The algorithm compresses the test patterns by overlapping patterns originally generated by an ATPG. The volume of test data stored in the embedded RAM is substantially lower than the compacted ATPG test data that are compressed by other compression method. The COMPAS algorithm spares the CPU time and CPU memory requirements; both are linearly dependent with the complexity of the tested core