T. Nishimura, H. Satoh, M. Tatsuki, A. Ohba, S. Hine, K. Uga, Y. Kuramitsu
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引用次数: 0
Abstract
A 12 K-gate ECL (emitter-coupled logic) gate array with dedicated memory has been developed using 0.6-μm bipolar process technology. The memory is available for RAM or ROM storage. The gate array can also be used to implement a configurable RAM having internal cells
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