Physical design of polarity controllable transistors

Abstract

This chapter deals with the lack of electronic design automation (EDA) tools that would enable industrial adoption of functionally enhanced devices (FEDs), limiting the abilities we have to explore the true potential of these devices. More specifically, we focus on an embodiment of FEDs, namely, silicon nanowire field effect transistors (SiNWFETs) three independent gate FETs (TIGFETs). TIGFETs offer new properties for logic design, including compact XOR and majority gates. We present a tool-flow that utilizes well-known standard EDA tools for synthesis and placement and routing (P&R) in order to map modern real-world designs onto the SiNWFET technology and compare them with current complementary metal-oxide-semiconductor (CMOS) technology. Also, in this chapter, we give emphasis to the concept of structured ASIC (application-specific integrated circuit) (sASIC) design and combine it with the fabrication regularity that SiNWFETs demand. We evaluated the performance of the tool-flow using SiNWFET technology by a series of runs, where the SiNWFET always outperformed the reference technology of FinFETs at 22 nm node, in terms of delay being up to ~35% faster and for exclusive OR (XOR)-dominated designs being ~15% smaller.