The book chapter provides a brief overview of some of the prominent features of non-carbon 2D materials that are currently being investigated and predicted to play significant role in the development of ultrathin electronic and optoelectronic devices in the coming years that could push the boundaries of current CMOS technology.
{"title":"Two-dimensional materials for functionality-enhanced devices","authors":"P. Gopalan, B. Sensale‐Rodriguez","doi":"10.1049/PBCS039E_CH3","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH3","url":null,"abstract":"The book chapter provides a brief overview of some of the prominent features of non-carbon 2D materials that are currently being investigated and predicted to play significant role in the development of ultrathin electronic and optoelectronic devices in the coming years that could push the boundaries of current CMOS technology.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124749914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The device characteristics of TIGFET technology, in particular the steep subthreshold slope (SS), have been studied in detail in this chapter. Notably, we have (1) summarized TIGFET's working principle and fabrication techniques, (2) reviewed experimental demonstrations of SSmin in TIGFETs with respect to voltage and temperature, and (3) performed device-level simulations to display and thoroughly explain the SS capabilities of TIGFETs with respect to channel length and voltage. Our results allow us to develop an in-depth explanation into the origin of steep SS and the potential limitations of SS in TIGFETs due to short-channel effects.
{"title":"Three-independent gate FET's super steep subthreshold slope","authors":"Jorge Romero-González, P. Gaillardon","doi":"10.1049/PBCS039E_CH6","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH6","url":null,"abstract":"The device characteristics of TIGFET technology, in particular the steep subthreshold slope (SS), have been studied in detail in this chapter. Notably, we have (1) summarized TIGFET's working principle and fabrication techniques, (2) reviewed experimental demonstrations of SSmin in TIGFETs with respect to voltage and temperature, and (3) performed device-level simulations to display and thoroughly explain the SS capabilities of TIGFETs with respect to channel length and voltage. Our results allow us to develop an in-depth explanation into the origin of steep SS and the potential limitations of SS in TIGFETs due to short-channel effects.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128936143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The book chapter highlights the application of MX2 type 2D materials to the polarity-controllable transistors, especially focused on the polarity control of carriers injected into TMDC materials. One of the bottlenecks in realization of polarity-controllable transistors consists in carrier injection of both electrons and holes into intrinsic semiconductor channel through Schottky junctions, and therefore, a novel method overcoming this bottleneck had been desired. Here, it was reviewed that the new kind of semiconducting materials of TMDCs has a promising feature for this purpose, and also, MoTe2, which is one of the TMDC family, has a great potential for polarity controllable transistors for its weak Fermi level pinning effect.
{"title":"Carrier type control of MX2 type 2D materials for functionality-enhanced transistors","authors":"S. Nakaharai","doi":"10.1049/PBCS039E_CH5","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH5","url":null,"abstract":"The book chapter highlights the application of MX2 type 2D materials to the polarity-controllable transistors, especially focused on the polarity control of carriers injected into TMDC materials. One of the bottlenecks in realization of polarity-controllable transistors consists in carrier injection of both electrons and holes into intrinsic semiconductor channel through Schottky junctions, and therefore, a novel method overcoming this bottleneck had been desired. Here, it was reviewed that the new kind of semiconducting materials of TMDCs has a promising feature for this purpose, and also, MoTe2, which is one of the TMDC family, has a great potential for polarity controllable transistors for its weak Fermi level pinning effect.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"6 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120828035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Back Matter","authors":"","doi":"10.1049/pbcs039e_bm","DOIUrl":"https://doi.org/10.1049/pbcs039e_bm","url":null,"abstract":"","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128518876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xifan Tang, P. Gaillardon, I. O’Connor, G. Micheli
In the quest to push further the Moore's scaling laws, intensive development efforts have been invested on seeking for alternatives to planar CMOS transistors at advanced technology nodes. In particular, recent years have witnessed the massive commercialization of the fin-basedfield effect transistors (FinFETs) at the 10, 14 and 22-nm technology nodes [1-3]. In addition to FinFET technology, several devices are currently investigated by following the trend toward 1D structures. Among them, carbon nanotubes FETs [4] and vertically stacked silicon nanowires FETs (SiNWFETs) [5] are promising extensions to current tri-gate FinFETs technology, which exploit the 1-D properties of their channels to exhibit superior performances. Moreover, these novel transistor technologies employ the gate-all-around (GAA) structure which can improve the electrostatic control of the channel, leading to a higher ION/IOFF ratio and reduced leakage current [6]. More than the performance improvement, these novel transistor technologies present another possible direction in pushing the Moore's scaling laws: functionality enhanced device. Especially at advanced technology nodes, transistors are strongly affected by Schottky contacts at the source and drain interfaces. As a result, transistors may operate with an ambipolar behavior, i.e., the device can exhibit nand p-type characteristics simultaneously. Indeed, to achieve pure n- and p-type polarity, the ambipolar behavior of the devices is typically suppressed through additional process steps. However, new design methodologies [7-9] have shown attractive opportunities in controlling the ambipolar phenomenon through programmable polarity devices. By engineering the source and drain contacts and by constructing independent doublegate structures, the device polarity can be electrostatically programmed to be either nor p-type. Such functionality-enhanced devices have been demonstrated using silicon [10,11] and carbon electronics [12,13]. In this chapter, we focus on a double-gate SiNWFET (DG-SiNWFET), built using a top-down fabrication flow [14].
{"title":"Ultrafine grain FPGAs with polarity controllable transistors","authors":"Xifan Tang, P. Gaillardon, I. O’Connor, G. Micheli","doi":"10.1049/PBCS039E_CH12","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH12","url":null,"abstract":"In the quest to push further the Moore's scaling laws, intensive development efforts have been invested on seeking for alternatives to planar CMOS transistors at advanced technology nodes. In particular, recent years have witnessed the massive commercialization of the fin-basedfield effect transistors (FinFETs) at the 10, 14 and 22-nm technology nodes [1-3]. In addition to FinFET technology, several devices are currently investigated by following the trend toward 1D structures. Among them, carbon nanotubes FETs [4] and vertically stacked silicon nanowires FETs (SiNWFETs) [5] are promising extensions to current tri-gate FinFETs technology, which exploit the 1-D properties of their channels to exhibit superior performances. Moreover, these novel transistor technologies employ the gate-all-around (GAA) structure which can improve the electrostatic control of the channel, leading to a higher ION/IOFF ratio and reduced leakage current [6]. More than the performance improvement, these novel transistor technologies present another possible direction in pushing the Moore's scaling laws: functionality enhanced device. Especially at advanced technology nodes, transistors are strongly affected by Schottky contacts at the source and drain interfaces. As a result, transistors may operate with an ambipolar behavior, i.e., the device can exhibit nand p-type characteristics simultaneously. Indeed, to achieve pure n- and p-type polarity, the ambipolar behavior of the devices is typically suppressed through additional process steps. However, new design methodologies [7-9] have shown attractive opportunities in controlling the ambipolar phenomenon through programmable polarity devices. By engineering the source and drain contacts and by constructing independent doublegate structures, the device polarity can be electrostatically programmed to be either nor p-type. Such functionality-enhanced devices have been demonstrated using silicon [10,11] and carbon electronics [12,13]. In this chapter, we focus on a double-gate SiNWFET (DG-SiNWFET), built using a top-down fabrication flow [14].","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114295951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Giovanni V. Resta, I. Radu, G. Micheli, P. Gaillardon
The book chapter is dedicated to polarity-controllable devices fabricated with two dimensional (2D) semiconducting tungsten diselenide (WSe2). The chapter is organized as follows: first, a general introduction on 2D materials is presented, followed by a section dedicated to summarize the state of the art in the growth of 2D materials. The concept of ambipolarity is then introduced, and the main experimental results on WSe2 ambipolar devices are presented. We transition then to the core part of the chapter describing recent advances in polarity-controllable transistors fabricated with ambipolar WSe2. We then focus on quantum transport simulations carried out to assess the performances of the devices at ultra-scaled gate lengths. We conclude with a summary, highlighting the main concept presented.
{"title":"Wse2 polarity-controllable devices","authors":"Giovanni V. Resta, I. Radu, G. Micheli, P. Gaillardon","doi":"10.1049/PBCS039E_CH4","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH4","url":null,"abstract":"The book chapter is dedicated to polarity-controllable devices fabricated with two dimensional (2D) semiconducting tungsten diselenide (WSe2). The chapter is organized as follows: first, a general introduction on 2D materials is presented, followed by a section dedicated to summarize the state of the art in the growth of 2D materials. The concept of ambipolarity is then introduced, and the main experimental results on WSe2 ambipolar devices are presented. We transition then to the core part of the chapter describing recent advances in polarity-controllable transistors fabricated with ambipolar WSe2. We then focus on quantum transport simulations carried out to assess the performances of the devices at ultra-scaled gate lengths. We conclude with a summary, highlighting the main concept presented.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129766957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this book chapter the authors show device metric predictions as determined by device simulations and present experimental demonstrator results in terms of fabrication and electrical characterization, respectively. Measurements and simulations show that in comparison to Si RFETs, the supply voltage can be reduced by a factor of 2 and dynamic power consumption can be ~4 times lower compared to silicon-based RFETs. In addition, on-currents can be boosted by up to a factor of 10 without degradation of capacitances, bringing a benefit in the intrinsic delay. Performance and power consumption metrics were extracted for different device geometries and benchmarked with modern conventional devices. The authors show that scaled Ge RFETs are competitive compared to modern low standby and low operating power technologies. The performance boosting at the device level combined with the circuit capabilities of RFETs holds the promise of enabling new circuit applications.
{"title":"Germanium-based polarity-controllable transistors","authors":"W. Weber, J. Trommer, A. Heinzig, T. Mikolajick","doi":"10.1049/PBCS039E_CH2","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH2","url":null,"abstract":"In this book chapter the authors show device metric predictions as determined by device simulations and present experimental demonstrator results in terms of fabrication and electrical characterization, respectively. Measurements and simulations show that in comparison to Si RFETs, the supply voltage can be reduced by a factor of 2 and dynamic power consumption can be ~4 times lower compared to silicon-based RFETs. In addition, on-currents can be boosted by up to a factor of 10 without degradation of capacitances, bringing a benefit in the intrinsic delay. Performance and power consumption metrics were extracted for different device geometries and benchmarked with modern conventional devices. The authors show that scaled Ge RFETs are competitive compared to modern low standby and low operating power technologies. The performance boosting at the device level combined with the circuit capabilities of RFETs holds the promise of enabling new circuit applications.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This chapter deals with the lack of electronic design automation (EDA) tools that would enable industrial adoption of functionally enhanced devices (FEDs), limiting the abilities we have to explore the true potential of these devices. More specifically, we focus on an embodiment of FEDs, namely, silicon nanowire field effect transistors (SiNWFETs) three independent gate FETs (TIGFETs). TIGFETs offer new properties for logic design, including compact XOR and majority gates. We present a tool-flow that utilizes well-known standard EDA tools for synthesis and placement and routing (P&R) in order to map modern real-world designs onto the SiNWFET technology and compare them with current complementary metal-oxide-semiconductor (CMOS) technology. Also, in this chapter, we give emphasis to the concept of structured ASIC (application-specific integrated circuit) (sASIC) design and combine it with the fabrication regularity that SiNWFETs demand. We evaluated the performance of the tool-flow using SiNWFET technology by a series of runs, where the SiNWFET always outperformed the reference technology of FinFETs at 22 nm node, in terms of delay being up to ~35% faster and for exclusive OR (XOR)-dominated designs being ~15% smaller.
{"title":"Physical design of polarity controllable transistors","authors":"O. Zografos, P. Gaillardon, G. Micheli","doi":"10.1049/PBCS039E_CH9","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH9","url":null,"abstract":"This chapter deals with the lack of electronic design automation (EDA) tools that would enable industrial adoption of functionally enhanced devices (FEDs), limiting the abilities we have to explore the true potential of these devices. More specifically, we focus on an embodiment of FEDs, namely, silicon nanowire field effect transistors (SiNWFETs) three independent gate FETs (TIGFETs). TIGFETs offer new properties for logic design, including compact XOR and majority gates. We present a tool-flow that utilizes well-known standard EDA tools for synthesis and placement and routing (P&R) in order to map modern real-world designs onto the SiNWFET technology and compare them with current complementary metal-oxide-semiconductor (CMOS) technology. Also, in this chapter, we give emphasis to the concept of structured ASIC (application-specific integrated circuit) (sASIC) design and combine it with the fabrication regularity that SiNWFETs demand. We evaluated the performance of the tool-flow using SiNWFET technology by a series of runs, where the SiNWFET always outperformed the reference technology of FinFETs at 22 nm node, in terms of delay being up to ~35% faster and for exclusive OR (XOR)-dominated designs being ~15% smaller.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this book chapter, a detailed explanation is given for the introduction of TIGFET devices into the BCB methodology. The fundamental principles of TIGFET technology are presented. The intrinsic device model under consideration is described and the basic circuit-level opportunities are investigated. The equations for area, delay, energy, and power for the various circuits are listed and the results are outlined and thoroughly examined.
{"title":"BCB benchmarking for three-independent-gate field effect transistors","authors":"Jorge Romero-González, P. Gaillardon","doi":"10.1049/PBCS039E_CH10","DOIUrl":"https://doi.org/10.1049/PBCS039E_CH10","url":null,"abstract":"In this book chapter, a detailed explanation is given for the introduction of TIGFET devices into the BCB methodology. The fundamental principles of TIGFET technology are presented. The intrinsic device model under consideration is described and the basic circuit-level opportunities are investigated. The equations for area, delay, energy, and power for the various circuits are listed and the results are outlined and thoroughly examined.","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122476320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For more than four decades, the semiconductor industry answered the demand for an increasingly higher level of integration and performance by following Moore's law [1], which predicts that the number of transistors and thus the complexity of circuits that can be integrated economically doubles every 18-24 months. Moore's law led us today to manufactured devices with dimensions of few tens of nanometers [2-5]. However, while the reduction of device dimensions increases the computing density, i.e., the maximal possible number of computations per unit area and time, the research community commonly admits that Moore's law is at its twilight and that innovations are required toward a more sustainable route [6-8].
{"title":"Introduction to functionality-enhanced devices","authors":"P. Gaillardon","doi":"10.1049/pbcs039e_ch1","DOIUrl":"https://doi.org/10.1049/pbcs039e_ch1","url":null,"abstract":"For more than four decades, the semiconductor industry answered the demand for an increasingly higher level of integration and performance by following Moore's law [1], which predicts that the number of transistors and thus the complexity of circuits that can be integrated economically doubles every 18-24 months. Moore's law led us today to manufactured devices with dimensions of few tens of nanometers [2-5]. However, while the reduction of device dimensions increases the computing density, i.e., the maximal possible number of computations per unit area and time, the research community commonly admits that Moore's law is at its twilight and that innovations are required toward a more sustainable route [6-8].","PeriodicalId":270370,"journal":{"name":"Functionality-Enhanced Devices An alternative to Moore's Law","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129615004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：