JTAG/Boundary Scan for Built-In Test

Abstract

Poor system reliability, combined with frequent failures of Built-In Test (BIT), may cause crew to undertake missions with undetected faults. Further, the need for rapid field repair, combined with line-replaceable unit (LRU) endemic fault isolation, dictates a new approach to system test. The use of JTAG-based boundary-scan test (BST), embedded on-board without the need for external physical hardware probes, cabling and fixturing, is described to address this issue. This paper details the application of JTAG for BIT, Test Access Port (TAP) controller firmware requirements, BST library Application Program Interface (API), and hardware design requirements.