A non-ICL UVM approach to verifying DFx IJTAG network and its pros and cons v/s the ICL-PDL approach

Abstract

An alternate XML based approach to ICL-PDL, to verifying DFx controller in an IJTAG network using UVM testbench i.e. scalable from block to full-chip. Current paper presents an overview of challenges with the standard ICL-PDL approach and how an XML based approaching leveraging the perks of using SV UVM based testbench can help overcome them. It draws parallels between the two and delineates the added advantages of using non-ICL approach as opposed to ICL-PDL when it comes to verifying DFx IJTAG network. Our main idea was to reuse UVM testbench for DFx controller verification. This approach helped in quick debugs, extracting code coverage and developing a common verification platform for functional and DFT components. This infrastructure helped us in chip level repair and verification whereas typical ICL-PDL based approach takes longer iterations for failure debug.