Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171799
Ronak Dham, Harish Gumudavelli
An alternate XML based approach to ICL-PDL, to verifying DFx controller in an IJTAG network using UVM testbench i.e. scalable from block to full-chip. Current paper presents an overview of challenges with the standard ICL-PDL approach and how an XML based approaching leveraging the perks of using SV UVM based testbench can help overcome them. It draws parallels between the two and delineates the added advantages of using non-ICL approach as opposed to ICL-PDL when it comes to verifying DFx IJTAG network. Our main idea was to reuse UVM testbench for DFx controller verification. This approach helped in quick debugs, extracting code coverage and developing a common verification platform for functional and DFT components. This infrastructure helped us in chip level repair and verification whereas typical ICL-PDL based approach takes longer iterations for failure debug.
{"title":"A non-ICL UVM approach to verifying DFx IJTAG network and its pros and cons v/s the ICL-PDL approach","authors":"Ronak Dham, Harish Gumudavelli","doi":"10.1109/ITCIndia49857.2020.9171799","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171799","url":null,"abstract":"An alternate XML based approach to ICL-PDL, to verifying DFx controller in an IJTAG network using UVM testbench i.e. scalable from block to full-chip. Current paper presents an overview of challenges with the standard ICL-PDL approach and how an XML based approaching leveraging the perks of using SV UVM based testbench can help overcome them. It draws parallels between the two and delineates the added advantages of using non-ICL approach as opposed to ICL-PDL when it comes to verifying DFx IJTAG network. Our main idea was to reuse UVM testbench for DFx controller verification. This approach helped in quick debugs, extracting code coverage and developing a common verification platform for functional and DFT components. This infrastructure helped us in chip level repair and verification whereas typical ICL-PDL based approach takes longer iterations for failure debug.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171795
S. Menon, V. Murugan
High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.
{"title":"Validating and Characterizing a 2.5D High Bandwidth Memory SubSystem","authors":"S. Menon, V. Murugan","doi":"10.1109/ITCIndia49857.2020.9171795","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171795","url":null,"abstract":"High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/itcindia49857.2020.9171783
{"title":"ITC India 2020 Author Index","authors":"","doi":"10.1109/itcindia49857.2020.9171783","DOIUrl":"https://doi.org/10.1109/itcindia49857.2020.9171783","url":null,"abstract":"","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117044392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/itcindia49857.2020.9171784
{"title":"ITC India 2020 Preface","authors":"","doi":"10.1109/itcindia49857.2020.9171784","DOIUrl":"https://doi.org/10.1109/itcindia49857.2020.9171784","url":null,"abstract":"","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134505532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171790
J. Popat, U. Mehta, M. Upadhyay
The AES is used in portable devices for secure communication. The AES is incorporated with scan-chains to make it testable. However, it poses security vulnerability since AES cipher can be attacked to recover private key. We propose a novel countermeasure, Hash based secure scheme, to prevent such attack.
{"title":"A Hash based Secure Scheme (HSS) against scanbased attacks on AES cipher","authors":"J. Popat, U. Mehta, M. Upadhyay","doi":"10.1109/ITCIndia49857.2020.9171790","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171790","url":null,"abstract":"The AES is used in portable devices for secure communication. The AES is incorporated with scan-chains to make it testable. However, it poses security vulnerability since AES cipher can be attacked to recover private key. We propose a novel countermeasure, Hash based secure scheme, to prevent such attack.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133375936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171785
Subhajit Chatterjee, S. Roy, C. Giri, H. Rahaman
Three-dimensional integrated circuit (3DIC) is an emerging technology with significant benefits over conventional 2DIC. However, 3D ICs face several challenges. This work presents a thermal-aware test scheduling technique for 3DICs. A machine learning based thermal estimation method for 3D ICs has been proposed in this work. The proposed temperature prediction technique has been used to generate thermally safe test schedules for 3DICs. The proposed techniques implemented on ITC’02 benchmark circuits has shown promising results.
{"title":"Machine Learning based Temperature Estimation for Test Scheduling of 3D ICs","authors":"Subhajit Chatterjee, S. Roy, C. Giri, H. Rahaman","doi":"10.1109/ITCIndia49857.2020.9171785","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171785","url":null,"abstract":"Three-dimensional integrated circuit (3DIC) is an emerging technology with significant benefits over conventional 2DIC. However, 3D ICs face several challenges. This work presents a thermal-aware test scheduling technique for 3DICs. A machine learning based thermal estimation method for 3D ICs has been proposed in this work. The proposed temperature prediction technique has been used to generate thermally safe test schedules for 3DICs. The proposed techniques implemented on ITC’02 benchmark circuits has shown promising results.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116614656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171789
Utsav Jana, B. Kumar, Ankita Agarwal, Deepak Agrawal
We propose a secure compression architecture to enable state-of-the-art compression features in production testing. The proposed architecture has minimal area overheads and is resilient against major attack models.
{"title":"Concealing Test Compression Mechanisms from Security Attacks","authors":"Utsav Jana, B. Kumar, Ankita Agarwal, Deepak Agrawal","doi":"10.1109/ITCIndia49857.2020.9171789","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171789","url":null,"abstract":"We propose a secure compression architecture to enable state-of-the-art compression features in production testing. The proposed architecture has minimal area overheads and is resilient against major attack models.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126094885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171792
Shan Pavan Pani Krishna Garapati, Sayandeep Sanyal, A. Patra, P. Dasgupta, M. Bhattacharya
With the increasing complexity of analog circuits in modern Systems on Chip (SOC), and their applications in safety-critical domains, the task of manufacturing fault-free SOCs is becoming more complex. The SOCs need to be designed to be more robust to parametric deviations caused during the fabrication process, any external disturbance or over a period of time due to ageing. In this paper, we propose a novel approach for ranking the transistors in an analog circuit based on their robustness to parametric deviations. We define the concept of fault vulnerability and introduce an associated quantitative measure to develop the ranking. We use time-efficient AC analysis along with a binary search technique for computing this measure. We carry out experiments on some circuits designed in-house and on three of the recently proposed ITC’17 AMS benchmarks. The results indicate that the proposed approach is computationally efficient and quite effective in ranking the transistors in terms of their fault vulnerability.
{"title":"Fault Vulnerability Ranking of Transistors in Analog Integrated Circuits using AC Analysis","authors":"Shan Pavan Pani Krishna Garapati, Sayandeep Sanyal, A. Patra, P. Dasgupta, M. Bhattacharya","doi":"10.1109/ITCIndia49857.2020.9171792","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171792","url":null,"abstract":"With the increasing complexity of analog circuits in modern Systems on Chip (SOC), and their applications in safety-critical domains, the task of manufacturing fault-free SOCs is becoming more complex. The SOCs need to be designed to be more robust to parametric deviations caused during the fabrication process, any external disturbance or over a period of time due to ageing. In this paper, we propose a novel approach for ranking the transistors in an analog circuit based on their robustness to parametric deviations. We define the concept of fault vulnerability and introduce an associated quantitative measure to develop the ranking. We use time-efficient AC analysis along with a binary search technique for computing this measure. We carry out experiments on some circuits designed in-house and on three of the recently proposed ITC’17 AMS benchmarks. The results indicate that the proposed approach is computationally efficient and quite effective in ranking the transistors in terms of their fault vulnerability.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"88 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122980086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ITCIndia49857.2020.9171788
Dev Narayan Yadav, K. Datta, I. Sengupta
One major operation in neuromorphic computing is vector-matrix multiplication (VMM), which is required during training and inference phases, and is expensive in terms of power consumption and latency. Hardware accelerators using emerging technologies like memristor crossbars can be used to speed up the process. Various faults in the crossbar can introduce errors in VMM computation. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power and delay. In this paper the impact of faults on memristor-based crossbars are explored to analyze the overall accuracy of VMM operations. It has been observed that in presence of limited number of faults, the accuracy is not significantly affected. However, as the number of faults increases, the error in computation also increases. The proposed approach works in two phases, high-level fault detection and low-level fault detection. In the first phase, the percentage of stuck-at faults in the crossbar is identified, and if it lies below a threshold the second phase is skipped. In the second phase, an efficient method to identify the exact location of the faults is used. The approach required less number of read/write operations as compared to existing works in the literature.
{"title":"Analyzing Fault Tolerance Behaviour in Memristor-based Crossbar for Neuromorphic Applications","authors":"Dev Narayan Yadav, K. Datta, I. Sengupta","doi":"10.1109/ITCIndia49857.2020.9171788","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171788","url":null,"abstract":"One major operation in neuromorphic computing is vector-matrix multiplication (VMM), which is required during training and inference phases, and is expensive in terms of power consumption and latency. Hardware accelerators using emerging technologies like memristor crossbars can be used to speed up the process. Various faults in the crossbar can introduce errors in VMM computation. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power and delay. In this paper the impact of faults on memristor-based crossbars are explored to analyze the overall accuracy of VMM operations. It has been observed that in presence of limited number of faults, the accuracy is not significantly affected. However, as the number of faults increases, the error in computation also increases. The proposed approach works in two phases, high-level fault detection and low-level fault detection. In the first phase, the percentage of stuck-at faults in the crossbar is identified, and if it lies below a threshold the second phase is skipped. In the second phase, an efficient method to identify the exact location of the faults is used. The approach required less number of read/write operations as compared to existing works in the literature.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126326217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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